MIPS32 1074K Coherent Processing System

• Foundry process independent, fully-synthesizable, multiprocessor IP supporting very high frequency implementations with commercial, non-custom standard cells and memories
• Cache coherent multiprocessing system supporting configurations with up to 4 cores
• Uses enhanced version of 15-stage superscalar, OoO 74K series core as base CPU, making it an ideal high-performance multiprocessing platform for Web-connected consumer products and highly-integrated home/residential gateways
• Provides additional 20-30% per core performance on JavaScript and Web-connected applications relative to earlier releases of 74K core RTL
• Supported by a broad ecosystem of application software and operating systems

A complete system for coherent multiprocessing, including:

• 1 to 4 1074K "base" cores
• 1074K base core = 74K superscalar, out-of-order high-performance processor with 15-stage pipeline, and cache coherence structures added for interface to Coherence Management unit
• Coherence Management (CM) unit – high throughput coherence fabric supporting 256-bit wide buses internally on key datapaths, as well as external read and write data interfaces to L2 cash and through to rest of system logic in SoC implementation
• I/O Coherence Unit (IOCU) – hardware acceleration for I/O coherence, offloading software implementation on CPUs
• Cluster Power Controller (CPC) – multicore power gating, clock gating, and reset management
• Global Interrupt Controller (GIC) – system and inter-processor interrupt controller
• EJTAG/PDtrace™ block for advanced debug/trace of complete coherent system

Floating Point Unit (FPU)

• MIPS 32® 1074Kf™ core version has IEEE 754-compliant FPU per core, compliant to MIPS® 64-bit FPU architecture
• Supports single- and double-precision data types
• Separate in-order, dual-issue pipeline decoupled from integer pipeline in each core

Coherency Management (CM) Unit

• Manages coherency using the MESI protocol
• Maximized throughput for multicore cluster supported by:
• 256-bit wide read and write buses (4x bus width between each core and CM) on key internal datapaths
• 256-bit wide read and write interfaces from CM to L2 cache and through to system interconnect
• L1 cache-to-cache transfers, speculative reads to external memory, and globalized cache operations
• Global Configuration Registers (GCRs) for configuring/controlling CM scheme

Cluster Power Controller (CPC)

• Provides highly scalable performance/power management via shutdown and bring up of one or more cores in the coherent processing system via clock or voltage island control
• Works in conjunction with each core implemented in a separate power domain

I/O Coherence Unit (IOCU)

• Bridges non-coherent I/O peripheral transfer and makes transactions coherent
• Supports per-transaction attributes for snooping L1 caches, L1+L2 caches, or non-coherent transactions, plus I/O prioritization

Global Interrupt Controller (GIC)

• Supports system-level interrupts; inter-processor interrupts
• Routes interrupts to a particular core or VPE
• Configurable # of system interrupts (up to 256)

Development Tools

• MIPSR Navigator ICS – Integrated Development Environment (IDE), software toolkit, cycle accurate and instruction accurate simulator models, EJTAG and PDtrace probes
• CodeSourcery - SG++ toolchains for MIPS

Both implementations optimized for speed (area and power-optimized specifications available upon request).

Achieved using free standard cells from TSMC and memories from Dolphin; quoted speeds are at worst case slow/slow corner, with signal integrity and production margins of 10% OCV and 25 ps clock jitter.

Note:
Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor and process and cell libraries.

Dual core configuration: 2 cores + coherence management unit with hardware IO coherence. Each core configured with 32K/32K caches, 32 entry dual TLB, and hardware floating point unit.