MIPS32 24K

• With an 8-stage pipeline and a maximum clock frequency exceeding 1400 MHz in 40nm, the 24K family of cores enable SoC designers to reduce product costs and speed time-to-market by giving them the performance headroom to implement more features now and upgrades in the future with software flexibility rather than rigid, fixed hardware.


• Cadence, Synopsys, Magma and other EDA industry leaders help minimize design time and offer a proven path to silicon by co-developing tailored SoC design methodologies. This couples the high-performance, low-power 24K cores with cutting-edge core hardening technologies.


• By standardizing the core interface on OCP (www.ocpip.org), the 24K cores accelerate time-to-market by enabling easy reuse of standard SoC IP. Memory controllers, bus interconnects and other standardized peripherals are now easily integrated through common on-chip interfaces.


• The highly-scalable 24K microarchitecture implements the industry-standard MIPS32 Release 2 architecture, which includes features such as enhanced bit-field manipulation, reduced interrupt latency and enhanced cache control.
• A rich environment of third-party tools and software support the 24K family of cores.

32-bit MIPS32® architecture

• 8-stage pipeline
• 32-bit address
• Vectored interrupts and support for external interrupt controller
• GPR shadow registers (optionally, one or three additional shadows can be added to minimize latency for interrupt handlers)

Floating Point Unit (FPU)

• Floating point version of core available
• IEEE std 754 compliant, supporting single and double precision calculations
• Contains 32 64-bit registers for more operations with less load/store overhead

DSP ASE Instructions

• 8-,16-and 32-bit SIMD instructions
• Saturating and fractional math
• Popular DSP operations, such as MAC, dot-product, absolute and complex-multiply
• Key features such as variable bit insert/extract and virtual circular buffers, complex multiply

MIPS16e™ Code Compression

• 16-bit encoding of 32-bit instructions to improve code density
• Special PC-relative instructions for efficient loading of addresses and constants
• SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines

Programmable Cache Size

• Individually configurable instruction and data caches, sizes of 0KB, 8KB, 16KB, 32KB, and 64KB
• 4-way set-associative
• Up to eight outstanding load misses
• Write-back and write-through support
• 32-byte cache line size

Scratchpad SPRAM Support

• Independent cache configuration
• 64b OCP 2.1 memory interface
• Can support arrays up to 1MB
• Separate RAMs for instruction and data

Memory Management Unit (MMU)

• 4-entry instruction, 8-entry data micro-TLBs
• Configurable 16/32/64 dual-entry joint TLB with variable page sizes
• Optional fixed mapping translation (FMT) for applications not requiring address mapping or protection

Bus Interface Unit (BIU)

• Implements the Open Core Protocol (OCP) Release 2.1
• 64-bit read and write data buses to efficiently transfer data between memory and L1 caches
• Supports a variety of CPU-to-system bus clock ratios to give greater flexibility for system implementation
• 4-entry write buffer

Integer Multiply/Divide Unit (MDU)

• Fully pipelined single-cycle repeat rate for 32x32 MAC instructions

Power Control

• Minimum frequency: 0 MHz
• Power-down (sleep) mode (triggered by the software WAIT instruction)
• Support for software-controlled clock divider
• Fine-grain clock gating

EJTAG debug

• Performance counters
• Support for single stepping
• Virtual instruction and data address breakpoints
• PC and data address and value tracing with trace compression

General Purpose Coprocessor (COP2) Interface

• 64-bit interface to a user defined coprocessor/li>

* DSP ASE available on 24KE core

24Kc™ & 24KEc Cores
Include a high-performance 32x32 multiply/divide unit and configurable MMU with TLB or fixed mapping.

24Kf™ and 24KEf Cores
Add hardware floating point support that is fully compliant with IEEE 754.

24K® and 24KE Pro Cores
4Kc/Kf Pro and 24Ec/KEf Pro cores feature the CorExtend™ capability.

All 24KE variants (24KEc, 24KEf, 24KEc/KEf Pro) include support for the DSP ASE.