MIPS32 34K Family
Imagination's MIPS32® 34K™ core family is a revolutionary implementation of the MIPS® MT ASE designed to exploit multi-threading in embedded applications. Processing multiple software threads in parallel, 34K cores mask the effect of memory latency to deliver instant 20-40% gains in system performance and cost savings, with a very modest increase in die size. The 34K core family also meets the real-time requirements of embedded applications by giving users the ability to allocate dedicated processing bandwidth to real-time tasks.
MIPS32 34K Summary
Lower System Costs
Higher application throughput enables several functions to be consolidated onto a single 34K core while preserving existing investments in software.
The 34K core can be configured with a maximum of two VPEs and nine TCs for ultimate design flexibility. Depending on the application, the 34K core can implement symmetric multiprocessing across two VPEs. Alternatively, each VPE can run a separate operating system.
A rich environment of third-party tools and software supports the 34K core family.
MIPS32 34K Features
- 9-stage pipeline
- 32-bit address
- 64-bit data paths to caches and external interface
MIPS MT ASE
- Support for up to 2 VPEs and 9 TCs
- Policy manager for QoS scheduling
- Inter-thread communication memory for efficient message and data transfer between TCs
MIPS DSP ASE
- 3 additional pairs of Hi/Lo accumulator registers
- Fractional data types (Q15, Q31)
- Saturating arithmetic
- SIMD instructions operate on 2×16b or 4×8b simultaneously
Floating Point Unit (FPU)
- Floating point version of core available
- IEEE std 754 compliant, supporting single and double precision calculations
- Contains 32 64-bit registers for more operations with less load/store overhead
- 16/32/64 dual-entry JTLB per VPE
- JTLBs are sharable under software control
- 4-9 entry MT-optimized ITLB; 8-entry DTLB
- Optional simple fixed mapping translation (FMT) mechanism
Programmable L1 Cache Sizes
- Individually configurable instruction and data caches, sizes of 0/8/16/32/64KB
- 4-way set associative
- Up to nine outstanding loads
- Write-back and write-through support
- Cache line locking support
Scratchpad RAM (SPRAM) support
- Separate RAMs for instruction and data
- Two 64-bit OCP interfaces for external DMA
Bus Interface Unit (BIU)
- OCP interface with 32-bit address and 64-bit data
- OCP interface runs at core/bus clock ratios of 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, or 10
Multiply/Divide Unit (MDU)
- 32×32 multiply with a repeat rate of one per clock cycle
Coprocessor 2 Interface
- 64-bit interface to a user-designed coprocessor
- Optional thread support
- Allows user to define and add instructions to the core at build time
- Minimum frequency: 0 MHz
- Power-down mode (automatic and program-controlled)
- Software-controlled clock divider
- Extensive use of fine-grained clock gating
- Support for single stepping
- Instruction address and data address/value breakpoints
- TAP controller is chainable for multi-CPU debug
- PC, data address and data value tracing with compression (PDtrace™)
MIPS16e™ Code Compression
- Reduces memory requirements by as much as 40 percent
MIPS32 34K Specifications
|Process||40nm G TSMC|
|Coremark/MHz ||2.97 |
|Frequency (MHz)||1454 (worst case)|
|Performance||1.6 (DMIPS/MHz) |
|Core Area (mm2)||0.46 Core only, extracted from full layout GDSII database|
|Power (mW/MHz)||0.11 Core only |
Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries. The DMIPS score is running on 1 thread only.
MIPS32® 34K® Core - Simplified Overview
TC: Thread Context - represents the user-state of the MIPS32® architecture.
VPE: Virtual Processing Element - represents the OS-only visible state of the MIPS32 architecture.
34Kc™ Core: The base core implementing the MIPS® MT and DSP ASEs.
34Kf™ Core: Adds hardware floating-point support that is fully compliant with the IEEE 754 specification.
34K® Pro Cores: 34Kc Pro and 34Kf Pro cores feature the CorExtend™ capability.