MIPS32 74K

The MIPS32® 74K® core family is the industry's first fully synthesizable processor IP to surpass 1.5 GHz in TSMC 40nmG process using industry standard libraries and EDA flows. The 74K® core family is based on a superscalar microarchitecture with out-of-order (OoO) instruction dispatch. The implementation features a 15-stage pipeline to achieve high synthesizable frequencies, and supports up to 4 instructions fetched per cycle, plus up to 4 instructions issued per cycle in the 74Kf core, the version in the family with a dual issue high performance floating point unit (FPU).

Imaginations' MIPS family is the leading processor architecture used in consumer entertainment and networking products in the home. Anticipating the emergence of Web-connected flat panel TVs, set top boxes (STB), Blu-ray DVD and related consumer devices, MIPS Technologies recently enhanced the 74K microarchitecture, with increased performance of 20-30% on Javascript, Flash®, and Web page rendering applications.

The innovative embedded microarchitecture also incorporates the MIPS® DSP Application Specific Extension (ASE) Rev2. These instructions, coupled with the 74K microarchitecture, dramatically boost signal processing performance up to 60% when compared to RISC implementations with original DSP ASE in previous generation architectures.

There are two versions available in the 74K core family – the 74Kc (integer core only) and the 74Kf (with high performance FPU), with both versions supporting a variety of configuration options, and use with a separately available SOC-it® L2 cache controller. In addition, the 1074K Coherent Processing System, a multi-core platform leveraging multiple 74K cores to provide new levels of performance for higher end digital home, networking and portable media applications is now available.

Resources

Architectural Strengths of the MIPS32® 74K® Core Family
MIPS32® 74Kc™ Processor Core Datasheet
MIPS32® 74Kf™ Processor Core Datasheet
Programming the MIPS32® 74K® Core Family
Programming the MIPS® 74K® Core Family for DSP Applications
MIPS32® 74K® Processor Core Family Software User’s Manual
74K BDTi DSP White Paper
Breaking the Gigahertz Speed Barrier with an Automated Flow Using Synopsys ICC Compiler

MIPS32 74K Summary

A 15-stage asymmetric dual-issue pipeline, out-of-order instruction dispatch/completion and fully synthesizable design gives SoC developers full flexibility to port the design across different processes and accelerate time-to-market
Two versions of the 74K family are available - 74Kc™ (standard) and 74Kf™ (high-performance Floating Point Unit)
Standard OCP bus interface provides backward-compatibility with existing 24K, 24KE and 34K cores
A rich ecosystem of third-party software and debug tools coupled with software and tools support from MIPS Technologies
Back-end EDA flow support for Cadence, Magma and Synopsys design tools

MIPS32 74K Features

Architecture

Superscalar asymmetric dual-issue pipeline with out-of-order dispatch and completion
128-bit wide access to the instruction cache and 64- or 128-bit wide access to the data cache
Up to 4 instructions fetched per cycle, and up to 4 instructions issued per cycle in 74Kf core with dual issue FPU
Combined majority branch predictor using three 256-entry BHT; 8-entry return prediction stack
CorExtend™ user-defined instruction set extensions
Multiply/divide unit to support maximum issue rate of one 32/32 multiply per clock
Low power consumption through the use of fine grain, block level, and top level clock gating
Support for Revision 2 of the MIPS32 DSP ASE
MIPS16e™ code compression
EJTAG debug 3.2 interface and PDtrace™ program and data trace

Floating Point Unit (FPU)

IEEE 754-compliant FPU, compliant to MIPS® 64-bit FPU architecture (74Kf version only)
Supports single- and double-precision data types
Separate in-order, dual-issue pipeline decoupled from integer pipeline

Bus Interface Unit

OCP version 2.1 interface with 32-bit address and separate 64-bit read and write data interfaces
OCP version 2.1 interface runs at core/bus clock ratios of 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, or 10 via a separate synchronous bus clock

Programmable MMU

16/32/48/64 dual-entry, dual-ported TLB shared by Instruction and Data MMU
4-entry ITLB (4KB, 1MB page size)
Optional simple Fixed Mapping Translation (FMT) mechanism

Programmable Cache Sizes

Configurable I-Cache (0-64KB) and D-Cache (0-64KB) sizes
4-way set-associative caches with write-back and write-through support
32-byte cache line size
Data scratchpad RAM support (4KB-1MB)
Extensions for front-side L2 cache

Development Tools

MIPS® Navigator ICS - IDE, software toolkit, MIPSsim™, EJTAG and PDtrace probes
CodeSourcery - SG++ toolchains for MIPS

MIPS32 74K Specifications

Process Node		TSMC 65GP	TSMC 40G	TSMC 40G
	Libraries	TSMC 10 track SVt	TSMC 12 track SVt	TSMC 12 track LVt
	Frequency	1.08 MHz	1.36 GHz	> 1.5 GHz
	Power (dynamic)	0.52 mW/MHz	0.32 mW/MHz	0.32 mW/MHz
	Total die area	2.5 mm²	1.38 mm²	1.38 mm²
Performance
	CoreMark/MHz	2.57	2.57	2.57
	DMIPS/MHz	2.03	2.03	2.03

Implementations optimized for speed (Area/Power optimized implementation data available upon request).

Achieved using free standard cells from TSMC and SVt memories from Dolphin Technologies.

Configuration:
2KB each for L1 inst and data caches; 64 jTLB entries (32 dual entry); FPU not included in above area.

Frequency:
Based on worst case, slow/slow corner synthesis, using PrimeTime tools and includes signal integrity (PTSI) plus production margins of 10% OCV and 50ps clock jitter (25 ps in 40nm).

Area:
Fully placed and routed floorplan, includes area for L1 caches.

Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor and process and cell libraries.

MIPS32® 74K® Core - Simplified Overview

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