MIPS32® M14K™ Family

A family of microMIPS® enabled processor cores providing high performance, low power solutions for real-time, cost sensitive MCU and embedded system applications.

• Efficient 5-stage pipeline, standard MIPS32® Release 3 Architecture, proven in millions of SoCs.
• Implements microMIPS®, a unified 16- and 32- bit ISA combining new and recoded MIPS32® instructions for 32-bit performance and near 16-bit code size
• Application-specific features for real-time performance, reduced interrupt latency, high performance embedded memory subsystems, virtual memory management, standard Bus Interface Unit and advanced power
• Advanced debug and profiling: expands on existing EJTAG-based debug/trace features with additional iFlowtrace™ capabilities, advanced program profiling, event analysis capabilities and real-time debug
• Comprehensive development support: supported by a complete microMIPS® and MIPS32®-compatible GNU software toolchain, MIPS® Navigator Integrated Component Suite (ICS), MIPS System Navigator™ debug probe and a FPGA-based development platform

Architecture

• MIPS32® Release 3 compatible 5-stage pipeline delivering 1.57 DMIPS/MHz
• MIPS32® and microMIPS® compatible instruction decoders
• Fixed Mapping Translation (FMT) Memory Management Unit (MMU) – M14K
• Configurable 16- or 32 dual entry joint TLB MMU or 4 entry I- and D- TLB MMU – M14Kc
• Configurable Multiply/Divide Unit, single cycle 32x16 and 2 cycle 32x32 multiply
• Thirty two 32-bit GPRs with an option for up to an additional 16 shadow sets of GPRs

microMIPS® Instruction Set Architecture

• Enhanced code compression ISA of combined 16- and 32-bit instructions
• Supports all existing MIPS32® instructions; adds new 16- and 32-bit instructions
• Configurable to support co-existence with MIPS32® decoder or standalone operation
• Includes support for all MIPS ASEs and CorExtend™ User Defined Instructions
• Supported by software toolchain and hardware development/debug systems

MCU Application Specific Extension

• Implements an enhanced interrupt handling scheme, supporting up to 8 interrupt pins in Vectored Interrupt mode and 255 interrupts in External Interrupt Controller mode
• Includes hardware features that reduce interrupt latency to 10 cycles
• Implements logic and new instruction (IRET) to automate and accelerate interrupt return handling operations
• Supports interrupt chaining
• Includes 2 new atomic-bit instructions

Memory Protection Unit (MPU) – M14K™

• Provides protection for up to 16 secure memory regions
• Configurable size, range and protection

Memory Management Unit (MMU) – M14Kc™

• 4 entry instruction and data TLB (ITLB/DTLB) with variable page sizes
• 16- or 32 dual entry joint TLB (JTLB) with variable page sizes
• Fixed or TLB-based MMU
• Security attribute: read-inhibit and execute-inhibit

Multiply & Divide Unit

• Single cycle 32x16 multiply, 2 cycle 32x32 multiply
• Divide operation latency between 11 and 34 clock cycles

Flash Memory Access Accelerator (optional)

• Implements a 2-line pre-fetch buffer to 'cache' flash memory contents
• Configurable for bit width and memory address range

Bus Interface Unit – Optional on M14K™

• Implements AMBA AHB-Lite interface
• Contains single 32-bit address bus and two unidirectional (R/W) data buses
• Single bus master with single burst mode support

SRAM-Style Interface – M14K™

• 32-bit address and data interface with single or multi latency support
• Configurable separate or unified instruction (I) and data (D) memory interface
• Supports connection to 8- and 16- bit memory devices, transaction abort, back-stalling, D- to I- redirection and lock/sync mechanism

Programmable cache controller – M14Kc™

• Individually configurable I- and D- caches, sizes range up to 64KB
• Direct mapped 2-, 3- or 4-way associative
• Write back and write-through modes

SPRAM Interface – M14Kc™, optional

• Replace 1-way of cache with up to 1Mbyte I- and D- Scratchpad RAM

Parity support - M14Kc™, optional

• Parity detection for I- and D-cache, I- and D- SPRAM

EJTAG Debug & Trace (Optional)

• Supports enhanced iFlowtrace with additional event trace modes
• Simple instruction & data breakpoint support - 2I/1D, 4I/2D, 6I/2D, 8I/4D
• Complex breakpoints, instruction & data, with conditional filtering supported
• Support for 2 Performance Counters (PCs) with multiple event type options
• PC and data address sampling: zero overhead, qualified read/write
• Fast Debug Channel provides a low overhead, high bandwidth bi-directional data transfer capability between the target and debug host/probe
• Supports optional 2-wire cJTAG
• Secure Debug support, prevents streaming instructions via EJTAG

Power Management

• Incorporates extensive fine clock gating
• Supports software controlled clock frequency divider
• Implements a Power Down mode initiated by a WAIT instruction

Extension Interfaces

• CP2 32-bit general purpose coprocessor interface
• CorExtend™ capability to develop user defined instructions (UDI)