MIPS32 M4K/4K Family
The MIPS32® M4K™/4K™ family includes MIPS32® 4K™, MIPS32® 4KSd™, MIPS32® 4KE™ and MIPS32® M4K™ 32-bit synthesizable processor cores.
MIPS32® M4K™ Core
The MIPS32® M4K™ 32-bit synthesizable core provides a highly performance-efficient, feature-rich solution for a broad range of real-time, cost-sensitive embedded system applications including microcontrollers, industrial control, home management systems, digital consumer, wireless networking, automotive and storage.
A wide range of configurable and optional features allow designers to optimize the core’s performance while reducing silicon area and power consumption.
Based on the well-proven MIPS® Release 2 architecture, the M4K™ core delivers superior DMIPS and CoreMark performance. In addition, the M4K™ core includes the MIPS16e™ Application Specific Extension (ASE), reducing code size by up to 40%.
Development of SoCs based on the M4K™ core is enhanced with a comprehensive ecosystem of MIPS™ design tools and partner support products.
MIPS32 M4K/4K Summary
- 5-stage pipeline architecture design, capable of operating over 400MHz; delivers 1.65 DMIPS/MHz and 3.1 CoreMark/MHz performance in MIPS32 mode.
- The M4K™ core has a build-time configurable external SRAM interface optimized for cacheless operation, enabling increased system performance and deterministic operation.
- The M4K™ core has built-in architectural features that enable reduced power consumption without affecting frequency or performance.
- CorExtend™ capabilities enable designers to create highly-differentiated SoC designs by adding their own instructions.
- The highly-configurable and synthesizable core enables flexibility for designers to include only those features necessary for their application.
- A rich environment of software and hardware tools support ease of design and verification.
MIPS32 M4K/4K Features
MIPS32® Release 2 Architecture
- 5-stage pipeline
- 1, 2, 4 or 8 sets of thirty-two 32-bit general-purpose registers
- Memory Management Unit with simple fixed mapping translation (FMT)
- Vectored interrupts and support for external interrupt controller
- Atomic interrupt enable/disable
User-defined instruction-set adds (CorExtend) Extensions
- Maintains full MIPS32® compatibility
- Supported by industry-standard development tools
- Single- or multi-cycle instructions
MIPS16e® ASE (Application Specific Extension)
- 16-bit encodings of 32-bit instructions to reduce code size by up to 40%
- Single- or multi-cycle transaction latency
- Separate or unified instruction and data memory interface
Integer Multiply/Divide Unit (MDU)
- Fast or area-efficient, configurable at build time
- Maximum issue rate of one 32x16 multiply per clock (fast MDU)
- Maximum issue rate of one 32x32 multiply every other clock (fast MDU)
General Purpose Coprocessor (COP2) Interface
- 32-bit interface to an external coprocessor
- Power-down mode (triggered by WAIT instruction)
- Support for software-controlled clock divider
- Support for extensive use of local gated clocks
- Support for single stepping
- Complex breakpoints and triggers, configurable at build time
- PC and data tracing (PDtrace)
- iFlowtrace mechanism for instruction addresses - compact trace block and efficient trace compression
MIPS32 M4K/4K Specifications
||200 - 414|
|Max Performance||671 (DMIPS) |
|Core Area (mm2)||0.12- 0.53|
||0.04 - 0.15 |
Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries. Quoted speeds are at production margins of +/- 5% OCV and 100ps clock jitter.