MIPS32 M4K/4K Family

• 5-stage pipeline architecture design, capable of operating over 400MHz; delivers 1.65 DMIPS/MHz and 3.1 CoreMark/MHz performance in MIPS32 mode.
• The M4K™ core has a build-time configurable external SRAM interface optimized for cacheless operation, enabling increased system performance and deterministic operation.
• The M4K™ core has built-in architectural features that enable reduced power consumption without affecting frequency or performance.
• CorExtend™ capabilities enable designers to create highly-differentiated SoC designs by adding their own instructions.
• The highly-configurable and synthesizable core enables flexibility for designers to include only those features necessary for their application.
• A rich environment of software and hardware tools support ease of design and verification.

MIPS32® Release 2 Architecture

• 5-stage pipeline
• 1, 2, 4 or 8 sets of thirty-two 32-bit general-purpose registers
• Memory Management Unit with simple fixed mapping translation (FMT)
• Vectored interrupts and support for external interrupt controller
• Atomic interrupt enable/disable

User-defined instruction-set adds (CorExtend) Extensions

• Maintains full MIPS32® compatibility
• Supported by industry-standard development tools
• Single- or multi-cycle instructions

MIPS16e® ASE (Application Specific Extension)

• 16-bit encodings of 32-bit instructions to reduce code size by up to 40%

SRAM Interface

• Single- or multi-cycle transaction latency
• Separate or unified instruction and data memory interface

Integer Multiply/Divide Unit (MDU)

• Fast or area-efficient, configurable at build time
• Maximum issue rate of one 32x16 multiply per clock (fast MDU)
• Maximum issue rate of one 32x32 multiply every other clock (fast MDU)

General Purpose Coprocessor (COP2) Interface

• 32-bit interface to an external coprocessor

Power Control

• Power-down mode (triggered by WAIT instruction)
• Support for software-controlled clock divider
• Support for extensive use of local gated clocks

EJTAG Debug

• Support for single stepping
• Complex breakpoints and triggers, configurable at build time
• PC and data tracing (PDtrace)
• iFlowtrace mechanism for instruction addresses - compact trace block and efficient trace compression

Development Tools

• Mentor® Embedded Sourcery™ CodeBench C/C++ GNU-based software toolchain
• MIPS System Navigator™ iFlowtrace™ probe, Navigator ICS, Navigator Console, MIPSsim™ simulator and SEAD™ -3 development board