MIPS 4Kc Hard IP Core
The MIPS32® 4Kc™ Hard Core is a technology-specific implementation of the synthesizable 32-bit MIPS32 4Kc core. The implementation is targeted for the SMIC 0.18um process. Chip developers or system OEMs who are building complex System-On-Chip ASIC devices can significantly reduce design time, resources,and time-to-market by using the 4Kc SMIC Hard Core.
4Kc Hard IP Cores Summary
- MIPS32® 4Kc® hard IP core offers performance of 190 MHz and allows designers to significantly reduce design time, efficiently use resources, and quickly get to market.
- Based on MIPS32 architecture for high performance.
- 8KB Instruction and 8KB Data cache
- TLB and register files arrays reduce power consumption without reducing application performance.
- Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging.
- Testability features include BIST and full scan
- All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture.
4Kc Hard IP Cores Features
Hard IP Cores
- 190 MHz at .18 SMIC with 5-layer or 6-layer metal
- 8K/8K Instructions and Data Caches
32-bit MIPS32 enhanced architecture
- 32-bit address and data paths
Integer multiply/divide unit
- Fast MDU
- Maximum issue rate of one 32x16 multiply per clock
- Maximum issue rate of one 32x32 multiply every other clock
- Minimum frequency: 0 MHz
- Power-down mode (triggered by WAIT instruction)
- TLB and register file arrays include use of clock gating
- Support for single stepping
- Virtual instruction and data address breakpoints
- MIPS® SDE GNU based toolchain, MIPSsim™ Instruction Set Simulator,
MIPS DSP Library. These tools are licensed for Windows, Linux and
Solaris operating systems
- A complete offering of third-party development tools
4Kc Hard IP Cores Specifications
||0.18µm SMIC process|
|Core Size||3.42 sq. mm including caches
*Frequency measured under worst case conditions (SS process corner, Vdd nom - 10%, Tj=125 oC) and with perfect input clock.