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MIPS 4KEc Hard IP Core

The MIPS32® 4KEc® Hard Cores are technology-specific implementation of the synthesizable 32-bit MIPS32 4KEc core. Available implementation targets include TSMC 0.18um CL018G process and TSMC 0.13um CL013G process. Chip developers or system OEMs who are building complex System-On-Chip ASIC devices can significantly reduce design time, resources, and time to-market by using 4KEc Hard Cores.

4KEc Hard IP Cores Summary

  • Hard IP cores allow designers to significantly reduce design time, efficiently use resources, and quickly get to market
  • Based on MIPS32 architecture for high performance
  • 8KB Instruction and 8KB writeback Data cache for more flexibility and higher performance
  • Instruction and data scratchpad interfaces available
  • A coprocessor 2 (COP2) interface enables easy coprocessor connection and support
  • Extensive clock gating reduces power consumption without reducing application performance
  • Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging
  • All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture
  • Testability features include BIST and full scan
  • Supports CorExtend capability which enables users to significantly enhance the value and competitive advantage of their SoC products

4KEc Hard IP Cores Features

Hard IP Cores

  • 175 MHz in .18µm G TSMC process
  • 233 MHz in .13µm G TSMC process

32-bit MIPS32 enhanced architecture

  • 32-bit address and data paths
  • Memory management unit with TLB
  • Bit field instructions
  • Vectored interrupts

Memory-management unit

  • 32 dual-entry JTLB

Integer multiply/divide unit

  • Fast MDU
  • Maximum issue rate of one 32x16 multiply per clock
  • Maximum issue rate of one 32x32 multiply every other clock
  • Scratchpad Interface

General purpose coprocessor (COP2) interface

  • 32-bit interface to an external coprocessor

Power control

  • Minimum frequency: 0 MHz
  • Power-down mode (triggered by WAIT instruction)
  • Support for extensive use of local gated clocks

EJTAG debug

  • Support for single stepping
  • Virtual instruction and data address breakpoints

Development Support

  • MIPS® SDE GNU based toolchain, MIPSsim™ Instruction Set Simulator, MIPS DSP Library. These tools are licensed for Windows, Linux and Solaris operating systems
  • A complete offering of third-party development tools.

4KEc Hard IP Cores Specifications

Process0.13µm TSMC CL013G 0.18µm TSMC CL018G
Frequency* 233 MHz1 175 MHz1
Core Size2.5 sq. mm including caches3.98 sq. mm including caches

*Frequency measured under worst case conditions (SS process corner, Vdd nom - 10%, Tj=125 oC) and with perfect input clock.

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