BusBridge2 Module

Imagination's BusBridge™ 2 Module features an easily configurable, high-performance, low latency MIPS core interface to the AMBA™ AHB. The module supports all members of the M4K®, 4KE®, 24K®, 24KE™, 34K®, 74K®, 1004K® and 1074K® core families of MIPS32® high-performance synthesizable cores and allows easy integration of the cores into any AHB bus system. The interface is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs wishing to rapidly integrate a MIPS core into an AHB-based system.

The MIPS BusBridge 2 module is configurable, allowing the user to either implement a reduced AHB master without arbitration (AHB Lite) or a full AHB master supporting the complete AMBA AHB specification. The reduced master option is designed for a single master AHB system where speed and simplicity are the main design issues. If a multi-master AHB system is required, then the full MIPS BusBridge 2 configuration adds support for both arbitration and slaves using Split/Retry responses.

MIPS BusBridge 2 is designed to provide the lowest latency possible between the core and the AHB bus. In order to meet this requirement, the module can be configured both as an unregistered interface ("no latency") and as a registered interface (registered outputs for improved timing).

Features

• AMBA AHB 2.0 compliant
• Supports up to 15 bus masters
• All AMBA slave response are supported
• Pass-thru or Registered modes
• No added latency in pass-thru mode, peak throughput is only limited by the AMBA bus
• Multiple core to AMBA clock ratios supported (1:1, 2:1, 3:1, 4:1, 5:1 and 6:1)
• CPU Core interface (Supports EC or OCP)

Resources

BusBridge™ 2 Module Download v4.0 (564kB PDF)
MIPS® BusBridge™ 2 Module Errata v1.03 (37kB PDF)
MIPS® BusBridge™ 2 Module Users Manual v2.04 (274kB PDF)