Imagination's BusBridge 3 family of synthesizable functional blocks help SoC designers integrate MIPS32 CPU's into the most popular high performance chip bus hierachies. The function blocks support all members of the 24K, 24KE, 34K, 74K, 1004K and 1074K core families of MIPS32 high performance synthesizable CPU cores, facilitating low latency operations involving the AXI or OCP bus protocols. The function blocks are targeted at Semiconductor OEM's, ASIC developers, and System OEM's designing and building their own SoC's. Currently, the family consists of two products:
OCP2AXI Bridge & AXI2OCP Bridge
The OCP2AXI bridge permits the connection of the MIPS32 OCP interface to an AXI system bus. Transactions between the MIPS32 CPU and the high performance AXI bus are handled with little or no latency penalty with this small gate count, fully synthesizable core.
The OCP Splitter is a small, synthesizable function block with an OCP input that expands to two OCP outputs. Send and receive operations are all zero latency.
Both cores are fully synthesizable. Customers are free to modify the deliverables as they see fit, though they are responsible for the resultant functionality and any verification.
- AXI v 1.0 compliant
- OCP 2.1 Master to AXI 1.0 Slave
- 32 bit addressing
- 64 bit datapath
- 1 cycle latency on Request, zero latency on Response
- Uses AXI system clock
- AXI 1.0 Master to OCP 2.1 Slave
- OCP 2.1 compliant
- 1 OCP Master input, 2 OCP slave outputs
- User configurable address decode
- Configurable port priority
- Configurable flow control
- Zero latency
- Synthesizable Verilog
- Synopsys Design Compiler synthesis scripts
- Verilog Test Bench
- User's Guide