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MIPS interAptiv Multiprocessor Core Family

Imagination's interAptiv family is the latest generation of the MIPS family multi-threaded (MT), multi-core, 32-bit processors from MIPS. The use of MT, improvements to multi-core performance, and additional core enhancements for error correction and power management, make interAptiv among the most performance-efficient and feature-rich CPU core in its class.

With the interAptiv core, designers have access to two virtual processing elements (VPEs), or hardware threads, which appear as two complete processors to an SMP operating system. These threads efficiently use a shared execution pipeline resulting in very high efficiency in terms of area and power relative to competing cores in the same class, as measured by the industry-standard CoreMark™ benchmark. Threads can also be managed using the hardware scheduler and inter-thread communication features. High efficiency and access to thread-level management make the interAptiv core the ideal solution for applications that are highly threaded and require support for Quality of Service (QoS).

Next-generation SoCs are increasingly moving towards multi-core designs even in mid-range markets such as the entry-level smart phone market. The interAptiv core utilizes our latest multi-core interconnect, the 2nd generation Coherence Manager (CM2), which has an integrated L2 cache. The CM2 improves multi-core performance by simultaneously reducing latency and increasing bandwidth. The CM2 supports up to four interAptiv CPUs or eight virtual processors in a single, fully coherent, multi-processor system.

Product resources

interAptiv™ Multi-processor Core Family Product Brief (.pdf) v.0512 (995 KB)
Optimizing Performance, Power, and Area in SoC Designs Using MIPS® Multi-threaded Processors
MIPS32® interAptiv™ Multiprocessing System Datasheet
MIPS32® interAptiv™ Multiprocessing System Software User's Manual

Also, with the increasing amount of data being stored and transported to and from a variety of embedded client devices and storage infrastructure equipment, data reliability has become a growing requirement. The interAptiv core, which now has Error Correction Code (ECC) support on data memories, makes it a great fit for higher reliability applications such as RAID storage and automotive driver assistance.

Finally, the interAptiv core, with its robust ability to control power at both the cluster and core levels, makes power management a snap for SoC designers.

interAptiv Summary

  • Multi-threaded, multi-core processor – Implements MIPS’ Multi-threading (MT) application specific extensions which provide up to 8 virtual processors in a single coherent multi-core system
  • Complete multi-core system designed for high bandwidth
    • Coherence manager with integrated L2 cache controller delivers reduced access latencies
    • High system bandwidth supported with 256 internal data paths
    • L2 cache: 4-way set associative, supporting up to 8MB of memory and variable wait states
    • Up to two IO Coherency Units (IOCU) per coherent processing system
    • Cluster Power Controller (CPC) for per-CPU clock and voltage gating
    • 256-interrupt Global Interrupt Controller (GIC); interrupts assignable to individual VPEs/threads
  • Increased data reliability – ECC option on all data memories including L1 and L2 caches and scratchpad RAM
  • Comprehensive power management – leakage and dynamic power management features in cores and cluster
  • Advanced debug capabilities – PDtrace™ subsystem allows visibility to core- and cluster-level trace information
  • Application-optimized configurations – available in quad-core and dual-core offerings with floating point variants.

interAptiv Applications

The interAptiv multiprocessor core family can be used as a cost and area efficient midrange processor in a variety of networking, home entertainment, mobile and embedded applications.

Mobile Home Entertainment Networking Embedded
* Low-to mid-range  apps processor
* LTE baseband  controller

* Mainstream  DTV/STB/BD  processor
* Digital camera

* Broadband CPE
* Femtocell
* Smart gateway

* Auto collision  avoidance
* Auto powertrain

interAptiv Features

interAptiv Multi-processor Core

  • 32-bit MIPS32® Release3 Instruction Set Architecture
  • 9-stage pipeline delivering 3.2 Coremark/MHz and 1.7 DMIPS/MHz per core
  • Supports single- or dual-threaded operation per core
  • Uses Virtual Processing Elements (VPEs) for hardware multi-threading
  • Support for Revision 1 of MIPS32 DSP ASE
  • Extended Virtual Addressing (EVA) for better utilization of address space
  • ECC on data L1 cache and SPRAM
  • Core power reduction options including core clock shutdown during outstanding bus requests, intelligent way selection in instruction L1 cache and enabled 32-bit accesses of the data L1 cache
  • Available in dual processor and quad processor offerings and floating point variants

Floating Point Unit (FPU)

  • IEEE 754-compliant FPU, compliant to MIPS® 64-bit FPU architecture (floating point version only)
  • Supports single- and double-precision data types
  • Separate in-order, dual-issue pipeline decoupled from integer pipeline

2nd Generation Coherence Manager (CM2) Unit

  • System-wide Coherence Manager with integrated L2 cache
  • 8-way set associative L2 cache controller supporting 256 KB to 8 MB cache sizes with variable wait state control for 1:1 clock and optimal SRAM speed
  • I/O and interrupt coherence across all CPU cores
  • Supports up to four interAptiv cores or eight VPEs in a coherent cluster

I/O Coherence Unit (IOCU) – optional use

  • Bridges non-coherent I/O peripheral transfer and makes transactions coherent
  • Supports per-transaction attributes for snooping L1 caches, L1+L2 caches, or non-coherent transactions, plus I/O prioritization
  • Up to two IOCUs per coherent cluster

Global Interrupt Controller (GIC) – optional use

  • Supports system-level interrupts; inter-processor interrupts
  • Routes interrupts to particular core or VPE
  • Configurable number of system interrupts (up to 256)

Development Tools

  • MIPS Navigator™ debug probe, Navigator Console debug software and Navigator ICS (Integrated Component Suite)
  • Mentor® Embedded Sourcery™ CodeBench compiler toolchain
  • Imperas OVPsim Instruction Accurate (IA) models and software development kit
  • Bus functional model of the core

interAptiv Specifications

TSMC 40G interAptiv
Frequency (WCH, with margins) >1 GHz
Base Core area (core + FPU) 0.9mm2 / 1.1mm2
Benchmarks Coremark DMIPS
Score/MHz (per core) 3.2 1.7
Total Score (per core) 3350 1750
Score/mm2 (w/o FPU) ~3750 ~2000
Score/mW 20 10.6

Single base core configuration includes:

  • 32KB Data/Inst L1 caches
  • 2 Virtual Processing Elements (VPEs) per core
  • Coherent base core only, with and without FPU
  • Full multi-level TLB (I/D uTLBs + 64 entry JTLB)
  • PDtrace™ debug
  • TSMC 40G 12T SVt std cells + std SVt memories
  • WCH corner, 10% OCV + 25ps clock jitter margins

No LVt cells or voltage OD or POP used

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