MIPS M4K Hard IP Cores

• Hard IP cores allow designers to significantly reduce design time, efficiently use resources, and quickly get to market
• Based on MIPS32 architecture for high performance
• Extensive clock gating reduces power consumption without reducing application performance
• Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging
• All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture
• Testability features include BIST and full scan
• Supports CorExtend capability which enables users to significantly enhance the value and competitive advantage of their SoC products

Hard Microprocessor Cores

• 110 MHz in .18µm SMIC process – Area optimized
• 137 MHz in .18µm SMIC process - Speed optimized

32-bit MIPS32 enhanced architecture

• 32-bit address and data paths
• Memory management unit with FMT
• Bit field instructions
• Vectored interrupts

Memory-management unit

• Simple Fixed Mapping Translation mechanism

Integer multiply/divide unit

• Fast MDU / Slow MDU options
• Maximum issue rate of one 32x16 multiply per clock
• Maximum issue rate of one 32x32 multiply every other clock

Power control

• Minimum frequency: 0 MHz
• Power-down mode (triggered by WAIT instruction)
• Support for extensive use of local gated clocks

EJTAG debug

• Support for single stepping
• Virtual instruction and data address breakpoints

Development Support

• MIPS® SDE GNU based toolchain, MIPSsim™ Instruction Set Simulator, MIPS DSP Library. These tools are licensed for Windows, Linux and Solaris operating systems
• A complete offering of third-party development tools.

*Frequency measured under worst case conditions (SS process corner, Vdd nom- 10%, Tj=125 oC) and with perfect input clock