MIPS microAptiv Core Family

A high-performance, compact-footprint unified MCU/MPU and DSP embedded processor core

• Available in two versions:
• microAptiv MCU core - designed with application-specific features and real-time performance for microcontroller SoC development
• microAptiv MPU core - includes a cache controller and MMU facilitating embedded system designs executing operating systems that manage virtual memory (e.g. Linux and Android)
• Software compatible, superset enhancement of the M14K/c cores
• Retains all the features of the M14K/c cores
• Implements the MIPS DSP ASE revision 2, providing single-cycle throughput on DSP and Multiply/MAC instructions
• Executes a large set of SIMD instructions on 8 and 16-bit data types
• Implements microMIPS, a unified 16- and 32- bit ISA combining new and recoded MIPS32 instructions for 32-bit performance and near 16-bit code size
• Includes options to configure MIPS32 and microMIPS instruction decoders
• Supported by a comprehensive set of MIPS hardware/software development tools and a growing ecosystem of partner development and SoC design products

Architecture

• MIPS32 Release 3 compatible 5-stage pipeline delivering 1.57 DMIPS/MHz and 3.09 CoreMark/MHz performance
• Dual decoder supporting MIPS32 and microMIPS instruction execution
• Optimized integration of DSP ASE r2, implementing a dual pipeline design to facilitate independent ALU/Integer and Multiply instructions
• Fixed Mapping Translation (FMT) Memory Management Unit (MMU)
• Configurable 16- or 32 dual entry joint TLB MMU, or 4 entry I- and D- TLB MMU
• Enhanced Multiply/Divide Unit (MDU), supporting 32x32 MAC operations
• Thirty two 32-bit General Purpose Registers (GPRs) with an additional option for up to 16 shadow GPRs

microMIPS Instruction Set Architecture

• Configurable to operate standalone or in co-existence with MIPS32 ISA
• Enhanced code compression ISA of combined 16- and 32-bit instructions
• Supports all existing MIPS32 instructions; adds new 16- and 32-bit instructions
• Supported by ELF and Linux software toolchains and hardware development/debug systems

DSP Application Specific Extension

• Implements over 150 instructions, including 70 SIMD and 38 Multiply/MAC instructions
• Operates on 8/16/32-bit signed/unsigned integer and fractional data types
• Executes a range of arithmetic instructions with saturation and rounding option, and data packing/unpacking, compare/pick, load and accumulate operations
• Destination specified in the instruction can be either a GPR or Accumulator
• Provides an option for up to three additional Accumulators
• The associated enhanced MDU is capable of executing 32x32, 16x16, dual 16x16, dual 16x8 and dual 8x8 multiply operations

MCU Application Specific Extension

• Includes hardware features that reduce interrupt latency to 10 cycles
• Implements logic and new instruction (IRET) to automate and accelerate interrupt return handling operations
• Supports interrupt chaining

Memory Protection Unit

• Available on microAptiv MCU
• Provides protection support for up to 16 memory segments
• Configurable segment address, size and protection levels

Programmable Cache Controller

• Configurable I- and D- caches, sizes range up to 64KB
• Direct mapped 2-, 3- or 4-way associative
• Write-back and write-through modes

SRAM-Style Interface

• 32-bit address and data interface with single or multi-latency support
• Configurable separate or unified instruction (I) and data (D) memory interface
• Supports connection to 8- and 16-bit memory devices

Bus Interface Unit

• Implements AMBA AHB™-Lite interface standard
• Contains single 32-bit address bus and two unidirectional (R/W) data buses

EJTAG Debug & Trace (Optional)

• Support for 2-wire cJTAG debug interface
• A secure debug feature which prevents streaming instructions through the EJTAG port
• Supports enhanced iFlowtrace™ with additional event trace modes
• Simple instruction and data breakpoint support – 2I/1D, 4I/2D, 6I/2D, 8I/4D
• Support for 2 Performance Counters (PCs) with multiple event type options
• PC and data address sampling: zero overhead, qualified read/write
• Fast Debug Channel provides a low overhead, high bandwidth bi-directional data transfer capability between the target and debug host/probe

Power Management

• Incorporates extensive fine- grain clock gating
• Supports software controlled clock frequency divider
• Implements a Power Down mode initiated by a WAIT instruction

Expandability

• Optional co-processor (COP2) and CorExtend™ / User Defined Instruction (UDI) interfaces

microAptiv MCU Core

Note
Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries
* Production frequency, PTSI, +/- 5% OCV, 50/100ps clock jitter
** Floorplan area
*** Speed Optimized - microMIPS+MCU ASE+Fast MDU+Scan+Prefetech+AHB+Memory Protection
*** Area Optimized - microMIPS+MCU ASE+Fast MDU+Scan
Area optimized frequency can be lower than the target chosen

microAptiv MPU Core

Note
Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries
* Production frequency, PTSI, +/- 5% OCV, 50/100ps clock jitter
** Floorplan area
*** Speed Optimized - microMIPS+MCU ASE+Fast MDU+Scan+16 TLB MMU+AHB
Memory configuration - 8KB/8KB I/D Cache