MIPS proAptiv Superscalar Multiprocessor
Core Family

The proAptiv™ processor family delivers top line performance while being the most efficient CPU core in its class, making it ideal for both mobile and digital home applications in the rapidly growing connected consumer electronics market.

The proAptiv processor has achieved > 4.4 CoreMark/MHz on preliminary RTL with EEMBC™ certification, a score significantly higher than any published score for licensable IP cores in the industry. It also achieves 3.5 DMIPS/MHz, with both scores representing a leap in performance of over 70% compared to the previous high end of the MIPS® core product lineup.

The proAptiv processor delivers this performance in a much smaller silicon footprint than leading IP core alternatives, achieving these results in nearly half the silicon area, given a common process geometry, similar configurations and synthesis techniques used. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage against competing silicon.

Market Applications and Target Performance

¹Higher end frequencies readily achievable with use of more aggressive implementation techniques such as those outlined as not used in our baseline specifications.

Coherent Multi-Core Processor Features

• Superscalar, deeply OoO multi-core processor – MIPS' new high performance processor core in a coherent multi-core platform
• Complete multi-core system designed for maximum cluster-level bandwidth
• 2nd generation coherence manager (CM2) - higher performance through L2 cache integration and improvements to design
• Higher speeds and lower latencies for increased throughput
• High-bandwidth 256-bit internal data paths and external system interface
• L2 cache: 4-way set associative, up to 8MB of memory
• ECC option on L2$ RAM for higher data reliability
• Configurable wait states to RAM for optimal L2$ design
• Up to two IO Coherence Units (IOCU) per coherent processing system
• Cluster Power Controller (CPC) for voltage/clock gating per-CPU
• 256-interrupt Global Interrupt Controller (GIC)
• Advanced debug capabilities – PDtrace subsystem allows visibility to core- and cluster-level trace information
• Application-optimized configurations – Single and multi-core versions available

Base Core Features

• 32-bit MIPS32® Release 3 Instruction Set Architecture
• High-performance, 13-stage, wide issue, out-of-order (OoO) pipeline
• Quad instruction fetch per cycle
• Triple bonded dispatch per cycle
• Instruction peak issue of 4 integer and 2 FPU operations per cycle
• Sophisticated branch prediction scheme, plus L0/L1/L2 branch target buffers (BTBs), Return Prediction Stack (RPS), Jump Return Cache (JRC)
• Instruction bonding – merges two 32-bit cache accesses into one 64-bit access for in2x increase on memory-intensive data movement routines
• L1 cache size for Instruction and Data of 32KB or 64KB each, 4-way set associative
• Programmable Memory Management Unit (MMU)
• Enhanced Virtual Address (EVA) provides better utilization of 32-bit address space
• 1st level micro TLBs (uTLBs) – 16 entry inst TLB, 32 entry data TLB
• 2nd level TLBs – simultaneous access, variable fixed page sizes
• 64x2 entry VTLB, 512x2 entry 4-way set associative FTLB
• MIPS DSP Application Specific Extension, version 2
• 4 accumulator register pairs, fractional data types, saturating arithmetic
• SIMD instructions operate on 2x16b or 4x8b simultaneously
• New high-performance dual-issue Floating Point Unit (FPU) - optional
• IEEE-754 compliant
• Runs at 1:1 frequency with CPU core
• Lower latency on most FPU operations
• Improved double precision operation throughput
• More parallelism/dedicated schedulers => more ops sustained in-flight
• Power Management Features
• Multi-core cluster power controller (CPC):
• Register-based, visible to/controllable by operating system
• Per CPU voltage domain gating; per CPU clock gating
• Cluster level DVFS capable
• Core level
• Course and fine-grained clock gating throughout core
• Way prediction on data and instruction L1 caches
• Instruction and register-based sleep modes
• CorExtend® provides customization through user defined instruction set extensions
• EJTAG/PDtrace debug blocks and interface
• MIPS16e™ reduced code size ASE

Preliminary frequencies based on fully floorplanned dual core cluster-level implementation in worst- case slow corner silicon with margins, using foundry/readily available standard cell and memory IP.

Not used in implementation: custom IP, LVt cells, voltage overdrive (VOD), "POP" kit technology, typical corner silicon, frequency binning, or special design signoffs.

Results based on

Each base core configuration:

• 32KB Data/Inst L1 caches with parity, memory BIST
• New high-speed FPU
• Fully-featured MMU, (I/D uTLBs + 128 entry VTLB + 1024 entry FTLB)
• PDtrace™ debug

Multi-core cluster configuration:

• 32KB Data/Inst L1 caches with parity, memory BIST
• New high-speed FPU
• Fully-featured MMU, (I/D uTLBs + 128 entry VTLB + 1024 entry FTLB)
• PDtrace™ debug

Implementation libraries/parameters – speed optimized, based on:

• TSMC 40G 12T SVt standard cells + Dolphin or Synopsys/Virage SVt memories
• Worst case, slow corner silicon (WCH) with 10% OCV + 25ps clock jitter margins