Meta Processing

MIPS proAptiv Superscalar Multiprocessor
Core Family


The proAptiv™ processor family is part of the MIPS Aptiv™ generation of processor IP cores from Imagination, designed to deliver the compelling top-line performance required for tomorrow’s connected consumer electronics including smartphones, tablets, connected TVs and set-top boxes. proAptiv CPUs are based on a wide issue, deeply out-of-order (OoO) implementation of the MIPS32 architecture, and are available in single and multi-core product versions supporting up to six cores. The proAptiv family leverages a new base core microarchitecture, a new floating point unit (FPU), and an enhanced multi-core interconnect to deliver a major leap forward in performance over the previous generation of MIPS’ IP cores, while implementing in nearly the half the size of competing cores in the same process node.

Product resources

MIPS32 proAptiv Multiprocessing System Software User's Manual (pdf) (9Mb)
MIPS proAptiv Factsheet (pdf) (801Kb)

proAptiv Summary

The proAptiv™ processor family delivers top line performance while being the most efficient CPU core in its class, making it ideal for both mobile and digital home applications in the rapidly growing connected consumer electronics market.

The proAptiv processor has achieved 5.1 CoreMark/MHz per core with EEMBC™ certification, a score significantly higher than any published score for licensable IP cores in the industry. It also achieves 3.5 DMIPS/MHz, with both scores representing a leap in performance of over 70% compared to the previous high end of the MIPS® core product lineup.

The proAptiv processor delivers this performance in a much smaller silicon footprint than leading IP core alternatives, achieving these results in nearly half the silicon area, given a common process geometry, similar configurations and synthesis techniques used. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage against competing silicon.

proAptiv Applications

Market Applications and Target Performance

Mobile Digital Home
* High-end tablet / smartphone   application processor

* 1.0 to 1.71 GHz

* Single to quad cores

* High-end connected DTV / STB   application processor

* 1.0 to 2.01 GHz

* Single to quad cores

Networking Embedded
* 802.11ac residential gateway , 3G/4G   cell infrastructure control plane

* 1.0 to > 2.01 GHz

* Single to quad cores

* Automotive infotainment application   processor

* 1.0 to 1.5 GHz

* Single to Quad cores

1Higher end frequencies readily achievable with use of more aggressive implementation techniques and physical libraries.

proAptiv Benefits

  • Superscalar, OoO processor available in application-optimized single and multicore versions
  • Sophisticated branch prediction for performance on modern software workloads
  • Load/Store bonding for optimum data movement performance
  • EVA (Enhanced Virtual Addressing) –programmable virtual address map for optimal use of 32-bit address space
  • Industry leading benchmark and real world performance without an increase in area and power
  • Broad software and ecosystem support and mature toolchain
  • Available as synthesizable IP, for implementation in any process node, with standard cells and memories

proAptiv Features

Base Core Features

  • 32-bit MIPS32® Release 3 Instruction Set Architecture
  • High-performance, 16-stage, wide issue, out-of-order (OoO) pipeline
    • Quad instruction fetch per cycle
    • Triple bonded dispatch per cycle
    • Instruction peak issue of 4 integer and 2 FPU operations per cycle
    • Sophisticated branch prediction scheme, plus L0/L1/L2 branch target buffers (BTBs), Return Prediction Stack (RPS), Jump Return Cache (JRC)
    • Instruction bonding – merges two 32-bit cache accesses into one 64-bit access for 2x increase on memory-intensive data movement routines
  • L1 cache size for Instruction and Data of 32KB or 64KB each, 4-way set associative
  • Programmable Memory Management Unit (MMU)
    • Enhanced Virtual Address (EVA) provides better utilization of 32-bit address space
    • 1st level micro TLBs (uTLBs) – 16 entry inst TLB, 32 entry data TLB
    • 2nd level TLBs – simultaneous access, variable and fixed page sizes
      • 64x2 entry VTLB, 512x2 entry 4-way set associative FTLB
  • MIPS DSP Application Specific Extension, version 2
    • 4 accumulator register pairs, fractional data types, saturating arithmetic
    • SIMD instructions operate on 2x16b or 4x8b simultaneously
  • New high-performance dual-issue Floating Point Unit (FPU) - optional
    • IEEE-754 compliant
    • Full speed with CPU
    • Improved double precision operation throughput
  • Power Management Features
    • Multi-core cluster power controller (CPC):
      • Register-based, visible to/controllable by operating system
      • Per CPU voltage domain gating; per CPU clock gating
      • Cluster level DVFS capable
    • Core level
      • Course and fine-grained clock gating throughout core
      • Way prediction on data and instruction L1 caches
      • Instruction and register-based sleep modes
  • CorExtend® provides customization through user defined instruction set extensions
  • EJTAG/PDtrace debug blocks and interface
  • MIPS16e™ reduced code size ASE

Coherent Multi-Core Processor Features

  • Superscalar, deeply OoO multi-core processor – MIPS' new high performance processor core in a coherent multi-core platform
  • Complete multi-core system designed for maximum cluster-level bandwidth
    • 2nd generation coherence manager (CM2) - higher performance through L2 cache integration and improvements to design
      • Higher speeds and lower latencies for increased throughput
    • High-bandwidth 256-bit internal data paths and external system interface
    • L2 cache: 4-way set associative, up to 8MB of memory
      • ECC option on L2$ RAM for higher data reliability
      • Configurable wait states to RAM for optimal L2$ design
    • Up to two IO Coherence Units (IOCU) per coherent processing system
    • Cluster Power Controller (CPC) for voltage/clock gating per-CPU
    • 256-interrupt Global Interrupt Controller (GIC)
  • Advanced debug capabilities – PDtrace subsystem allows visibility to core- and cluster-level trace information
  • Application-optimized configurations – Single and multi-core versions available

proAptiv Specifications

Target TSMC 28HPM
Frequency 1 GHz - 2+ GHz*
CoreMark/MHz (per core) 5.1
Total CoreMark @ 1.5GHz > 7500 per core
DMIPS/MHz (per core) 3.5
Total DMIPS @ 1.5GHz > 5250 per core

Notes: Frequencies indicated are for fully floorplanned dual core implementation, ranging from 12T SVt area-optimized in worst case silicon corner, to 12T MVt speed-optimized typical corner silicon.

Each base core configuration:

  • 32KB Data/Inst L1 caches with parity, memory BIST
  • New high-speed FPU
  • Fully-featured MMU, using multi-level TLB (I/D uTLBs + 128 entry VTLB + 1024 entry FTLB)
  • PDtrace™ debug

Multi-core cluster configuration:

  • Dual fully-configured proAptiv cores per above
  • Coherence Manager + integrated 1MB L2$ w/ECC
  • One hardware IO Coherence Unit (IOCU) port
  • Cluster level PDtrace

Implementation libraries/parameters – speed optimized, based on:

  • TSMC 28HPM 12T standard cells + Synopsys memories
  • Worst case, slow-slow corner silicon (zero temp, WCZ) with 10% OCV + 25ps clock jitter margins, except where noted at typical silicon.


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