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MIPS64 Architecture

Imagination's MIPS64® architecture has been used in a variety of applications including game consoles, office automation and set-top boxes, and maintains popularity today in networking and telecommunications infrastructure applications. As design complexity and software footprints increase, the benefits of 64-bit computing become attractive to a broader set of applications including servers, next generation mobile and connected consumer devices and SOHO networking products.

The MIPS64 architecture provides a solid high-performance foundation for future MIPS processor-based development by incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs, and providing a seamless upgrade path from the MIPS32 architecture..

The MIPS32 and MIPS64 architectures incorporate important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing), enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

The MIPS64 architecture is based on a fixed-length, regularly encoded instruction set, and it uses a load/store data model. It is streamlined to support optimized execution of high-level languages. Arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation by keeping frequently accessed data in registers.

The architecture derives the privileged mode exception handling and memory management functions from the R4000 and R5000 class processors. A set of registers reflects the configuration of the caches, MMU, TLB, and other privileged features implemented in each core. A MIPS32 architecture compatibility mode allows running 32-bit code on the MIPS64 without changes. By providing backward compatibility, standardizing privileged mode, and memory management and providing the information through the configuration registers, the MIPS64 architecture enables real-time operating systems and application code to be implemented once and reused with future members of both the MIPS32 and the MIPS64 processor families.

Flexibility of high-performance caches and memory management schemes are strengths of the MIPS architecture. The MIPS64 architecture extends these advantages with well-defined cache control options. The size of the instruction and data caches can range from 256 bytes to 4 MB. The data cache can employ either a write-back or write-through policy. A no-cache option can also be specified. The memory management mechanism can employ either a TLB or a Block Address Translation (BAT) policy. With a TLB, the MIPS64 architecture meets the memory management requirements of Linux, Android™, Windows® CE and other historically popular operating systems.

The addition of data streaming and predicated operations supports the increasing computation needs of the embedded market. Conditional data move and data prefetch instructions are standardized, allowing for improved system-level data throughput in communication and multimedia applications.

Fixed-point DSP-type instructions further enhance multimedia processing. These instructions that include Multiply (MUL), Multiply and Add (MADD), Multiply and Subtract (MSUB), and "count leading 0s/1s," previously available only on some 64-bit MIPS processors, provide greater performance in processing data streams such as audio, video, and multimedia without adding additional DSP hardware to the system.

Powerful 64-bit floating-point registers and execution units speed the tasks of processing some DSP algorithms and calculating graphics operations in real-time. Paired-single instructions pack two 32-bit floating-point operands into a single 64-bit register, allowing Single Instruction Multiple Data operations (SIMD). This provides twice as fast execution compared to traditional 32-bit floating-point units. Floating point operations can optionally be emulated in software.

The MIPS64 architecture features both 32-bit and 64-bit addressing modes, while working with 64-bit data. This allows reaping the benefits of 64-bit data without the extra memory needed for 64-bit addressing. In order to allow easy migration from the 32-bit family, the architecture features a 32-bit compatibility mode, in which all registers and addresses are 32-bit wide and all instructions present in the MIPS32 architecture are executed.

MIPS64 Architecture Summary

  • The first 64-bit CPU architecture in the world, introduced in 1991
  • A well supported software ecosystem that has been built up over that time to support different market segments
  • Widely used in multiple markets - SOHO networking, office automation, networking/telecommunications infrastructure, next generation mobile devices, servers and more
  • 64-bit address space allows for very large memory systems
  • 64-bit registers allow for higher memory bandwidth
  • Seamless operation with MIPS32® - no mode-switching needed between 32-bit processing and 64-bit processing

MIPS64 Architecture Features

  • Fixed-sized 32-bit instructions allow easy instruction decode

  • 32 x 64-bit General Purpose Register file; optional shadow register sets

  • Robust load/store RISC instruction set with 3-operand instructions in most formats (3 registers, 2 registers + immediate), branch/jump options, and delayed jump instructions
    • Simple addressing modes allow for higher frequencies and simpler implementations
    • Flexible software management for stack operations
    • Delayed branches aid in efficient coding

  • No integer condition codes allows for easier superscalar implementations

  • Up to 64 bits of virtual address space; up to 59 bits of physical address space

  • Optional Modules of the Base Architecture
    • MIPS SIMD architecture (MSA) module provides more computational capability for a wide range of applications
    • Scalable Virtualization (VZ) module provides secure hardware virtualization
    • Multi-threading provides high throughput processing
    • DSP technologies for media processing

  • Support for 8-bit, 16-bit, 32-bit and 64-bit variables

  • Flexible software management of Page Table walk

  • Floating Point Specifications
    • Optional single and double-precision floating point support
    • IEEE-754-2008 Floating-Point specification Support
    • 32 x 64-bit Floating-Point Registers

  • Compatibility
    • Fully supports Big-Endian and Little-Endian systems
    • Fully MIPS I™ and MIPS II™ ISA compatible
    • Upward compatible with MIPS64 architecture

  • Specific Instructions
    • Enhanced with conditional move and data-prefetch instructions
    • Standardized DSP operations: multiply (MUL), multiply and add (MADD), and count leading 0/1s (CLZ/O)
    • Rotate instructions
    • Integer multiply, divide support
    • Bit-field insert/extract instructions

  • Interoperability with microMIPS™ ISA

  • Optional Memory Management Unit (MMU) with:
    • TLB or BAT address translation mechanisms
    • Programmable page size
    • Flexible software management of Page Table walk
    • Increased security with execute inhibit and read inhibit pages
    • Enhanced page-table handling
    • Virtual Memory segments with programmable attributes

  • Optional caches:
    • Instruction and/or data cache options
    • Write-back or write-through data cache options
    • Virtual or physical addressing

  • Enhanced JTAG (EJTAG) support for non-intrusive debug support

MIPS64 Architecture Specifications

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