Design optimization is perhaps one of the most talked about topics inside the semiconductor world right now. Recognizing the growing need among our silicon partners for a validated solution that provides the flexibility to optimize for power, performance or area (PPA) in SoC implementations, we have created the Design Optimization Kit (DOK) – a complete and versatile design optimization package from Imagination that allows our partners to choose various levels of optimization according to their individual requirements.

Imagination Design Optimization Kit | Imagination DOK

Unlike alternative solutions which go for an ‘all or nothing’ approach, our customers can obtain different levels of customization which include a combination of reference floorplans and/or reference flows from Imagination, based on libraries from industry leading EDA software providers.

An enhanced DOK with industry leading third party IP

On top of that, we offer the possibility of including the best third party IP available on the market from our technology partners. A great example of this is Imagination’s recent DOK IP launch for our PowerVR Series6 GPU cores. This package includes Synopsys’ new DesignWare® HPC (High Performance Core) Design Kit, which allows our PowerVR ‘Rogue’ GPU licensees to achieve significant reductions in power and area or important increases in frequency and performance.

PowerVR Series6 Design Optimization Kit | PowerVR Series6 DOK

To give you a rough idea of our results, the optimization work we’ve done for the PowerVR G61000 GPU core has so far led to a 25% decrease in dynamic power (based on static toggle rates) and up to 10% area savings, as well as up to 30% improvement in implementation turnaround time through a tuned design flow.

A complete package including documentation and design point examples

Included within the DOK is documentation detailing how implementation choices are made and their associated benefits so that customers can elect which aspects to replicate in their incumbent flow. This allows the customer to effetely explore differently PPA design points to address the needs of their SoC requirements.

All data provided will have been qualified to achieve the stated PPA targets stated along with intermediate metrics to aid predictable design closure.

To significantly reduce integration effort and maximize results we are using the latest high performance reference flows from leading EDA providers as the basis of our flow development work. This ensures that our mutual customers receive the very best tool flow independent of tool version, which is then supplemented with side files created by Imagination to further fine tune the flow based upon our design knowledge.

We are therefore effectively bringing together under one roof our engineering and IMGworks divisions, EDA companies and foundries to produce one, ease to reproduce flow.

Finally, in recognition that our customers floorplans may need to differ for our reference, we have made every effort to provide relative placement guidance to help mutual customers realise their own production floorplans in less iterations.

As you can see from the features above, we’ve kept the focus on designing a flexible solution for customers looking to use our DOK IP technology to optimize their designs even further, targeting an optimum balance of performance or power and area for their specific application.

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