MIPS OCI (On Chip Instrumentation) is a new flexible, modular debug architecture from Imagination for heterogeneous computing systems integrating multiple MIPS CPUs, and systems that combine MIPS CPUs with other CPU architectures. OCI comprises of modular interoperable debug IP components that can be selected to produce an optimal debug solution tailored to the needs of a specific SoC design.

The new OCI architecture has already been implemented for the MIPS Warrior I6400 and M6200/M6250 CPUs.

This debug architecture provides a more efficient solution that replaces the traditional arrangement of multiple JTAG TAPs in a single scan chain. This offers improved SoC debug effectiveness over traditional JTAG scan chains, and adds the ability to power down or clock gate cores without affecting debugging of the remaining powered up cores and the rest of the system.

An overview of the MIPS OCI components

The Debug Unit (DBU)

The Debug Unit (DBU) is represented in the diagram below.

MIPS OCI - Debug unit The MIPS Debug Unit

The DBU is designed to provide access to the cores and sub-components of a MIPS I-class or P-class Coherent Processing System via the internal ring bus and also provides other debug features and benefits:

  • Non-intrusive monitoring of the system and cores enabling access to some core state, and all global state, via the ring bus without having to halt any of the CPU cores.
  • A dedicated block of RAM to provide acceleration of common debug operations, which is critical in a complex multi-core and multi-threaded system.
  • Additional external interface adaptors can be used for debug access. Typically access would be via a probe, but the DBU facilitates another host CPU or an emulator transactor port:
    • 1 JTAG – four wire JTAG for a direct connection to a probe.
    • APB Slave Port – 32-bit peripheral bus for connecting to host CPUs, transactional models or third party debug access hardware.
The MIPS Debug Hub (DBH)

The MIPS Debug Hub (MDH) depicted in the diagram below is a standalone IP block used to connect APB compliant devices to JTAG probes, including Imagination’s new SysProbe range.

MIPS OCI - MIPS debug hubThe MIPS Debug Hub architecture

Support will also be provided by third party probe vendors including Lauterbach and Green Hills. The MDH provides three external connection options:

  • 1 JTAG – four wire JTAG for a direct connection to a probe.
  • 7 compact JTAG – two wire JTAG for a direct connection to a probe.
  • APB Slave Port – 32-bit peripheral bus for connecting to host CPUs and transactional models (in emulation).

The MDH enables connection for up to 32 legacy JTAG TAPs and support for monitoring power-gating of the cores in the system through a loop-through JTAG mux. The APB Master Port enables support for up to 16 cores on the APB bus.


Imagination provides further flexibility in its debug configuration options with a PDtrace to ATB convertor allowing integration of PDtrace capable cores into third party tracing systems.

An APB to JTAG convertor provides a broad array of connections and conversions from legacy JTAG devices or another on-system host CPU.

Support for MIPS CPUs

I-Class and P-Class CPUs

Warrior I-Class and P-Class cores from I6400 onward feature a Debug Unit (DBU) and a ring bus connecting all CPU cores, the coherency manager and other global subsystems.

M-Class CPUs

Newer M-Class warrior cores implement an APB interface for flexibility, providing direct access to debug registers for configuring breakpoints and trace hardware without having to halt the core.

Together with the latest Codescape SDK for development, debug and optimization, and the new Codescape SysProbes for fast and efficient debug, MIPS OCI provides a powerful end-to-end debug environment. For more information, visit our MIPS developer tools community page.

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