This year’s Embedded Technology conference in Japan is ground zero for a new revolution in mobile and embedded connectivity. The conference marks the launch of a range of Imagination’s Ensigma radio communications processors (RPUs) for smartphones, tablets, wearables, IoT and other connected products.
The configurable baseband IP cores we are announcing include:
- Ensigma C4511, which supports 802.11n 1×1, Bluetooth, and FM for affordable phones and wearables;
- Ensigma C4521, which offers 802.11ac 1×1, Bluetooth 4.0, and FM for smartphones, tablets and other similar devices;
- Ensigma C4531, providing 802.11ac 2×2, Bluetooth 4.0, and FM for tablets, ultrabooks, gaming consoles, smart TVs and embedded devices.
Whereas traditionally the Wi-Fi, Bluetooth and FM combo used to be a separate chip in the system, Ensigma RPUs offer a more cost-effective alternative, since the power efficient solution can be integrated onto the main SoC. SoC designers can now integrate all three connectivity standards in various configurations on the same chip with CPUs, GPUs, VPUs and other processors, offering a great solution for our customers.
Digital baseband integration leads to cheaper and more power efficient processors for mobile applications, pushing down Bill of Materials (BoM) costs and ushering in a new wave of applications for an improved mobile experience. By using our configurable Ensigma Wi-Fi/Bluetooth/FM solutions, we envision wristband or smart watch devices being able to transmit biometric information to your mobile phone or smart glasses streaming content from your multimedia hub. In fact, other standards such as Bluetooth 4.0 LE (Bluetooth Smart) can be licensed as standalone IP or in combo configurations. Wearables are the perfect example where customers can combine Bluetooth LE with FM for ultra low-power applications.
Furthermore, Ensigma RPUs feature an advanced hardware architecture that makes video buffering, slow downloads and dropped connections a thing of the past. This is because Ensigma enables better usage of bandwidth for all mobile devices, which is particularly important when streaming HD content over Wi-Fi. Complementing Ensigma’s hardware specifications, the new baseband combo IP cores implement advanced coexistence algorithms that enable you to have fewer dropped connections, better signal range and faster media streaming. Features of these algorithms include:
- Advanced scheduling algorithms based on Bluetooth TX/RX cycle prediction
- Coexistence-aware Carrier Sense, Packet Sync and Transmission
- Efficient baseband/MAC level information sharing to track frequency and signal threshold adaptation
- Multiple packet priorities for QoS across Bluetooth and Wi-Fi
- Optional shared antenna
- Support for standard 2, 3, 4 wire interface
The combination of an efficient architecture and a cleverly implemented software stack offers Ensigma the following unique advantages over competing solutions:
- Unified memory architecture for the lowest possible silicon footprint
- Aggressive reuse of DDR memory, reducing on-chip memory for data and program storage
- Removal of interface bottlenecks and processing requirements for USB/SDIO
- Reduction of pads/off-chip communication for increased power savings
- Better host power management for reduced overall system power consumption
What is the Ensigma RPU?
The Ensigma Series4 ‘Explorer’ RPU is a family of highly efficient programmable baseband IP for high data rate communication protocols (e.g. Wi-Fi 802.11ac), low bit rate communications (e.g. Bluetooth 4.0, ZigBee), and demodulation (TV, radio). Ensigma offers the best of both worlds: a fully programmable core designed as configurable hardware. This enables us to deliver custom IP for individual markets or combos that address a wide range of applications.
By using Ensigma Series4 RPUs, important savings in area and manufacturing costs can be achieved, especially for multi-mode applications. The Ensigma RPU architecture is based on hybrid programmable and configurable engines that provide field upgradability and efficient field debug, which makes them amenable for custom applications.
Because we’ve optimized all of our designs for SoC integration, system resources can be shared between different on-chip processors which reduces the requirements for on-chip memory for data and program storage. By licensing our PowerVR graphics processors (GPUs), PowerVR video/vision processors (VPUs), MIPS CPUs, Ensigma RPUs, and FlowCloud IP, system architects have access to the building blocks for tomorrow’s connected processors.
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