When selecting processor IP for connectivity or communication standards, most people compare fixed-function blocks vs. programmable (or software defined radio [SDR]) solutions in terms of three parameters:
- Die size
While the SDR-based approach provides better flexibility by virtue of its programmability, the challenge is that SDR processors have generally been known to be power hungry and less area efficient.
Ensigma Explorer RPUs represent a best of both worlds architecture that can be implemented in an area and power efficient system. In this article, I will delve deeper into our LTE Category 0 and Category 1 (Cat-0 and Cat-1) implementation for the Ensigma Explorer Series5 architecture.
LTE Cat-1 provides a data rate of up to 10 Mbps and allows significant reductions in on-chip processing power, clock speeds and memory requirements. This directly translates to reduced base band die size, power consumption, and cost. For IoT applications this allows module costs to fall below 3G module costs.
LTE Cat-0/M achieves speeds of up to 1 Mbps and is expected to further reduce cost and power consumption. However LTE Cat-0 is not expected to be ready for mass deployment until mid-2017.
Imagination’s LTE solutions feature Cat-0/1 hardware support. The LTE implementation has the Layer 1 (L1) ported on the Ensigma RPU and the Layer 2 (L2)/Layer 3 (L3) running on the host MCU (such as a MIPS M-class CPU).
In the following section, I wish to expand on expand on the optimizations we’ve made in terms of die size, power consumption and flexibility – all critical parameters for connectivity IP.
Die size optimizations
Within Ensigma Explorer RPUs, several hardware-level optimizations enable a direct reduction in die size. Some of the LTE specific accelerators included are:
- A complete uplink data channel (PUSCH) implementation
- A crypto and an FFT engine
- A Viterbi and turbo decoder
- PN Sequence Generators
- A de-mapper (including HARQ recombining)
Power Consumption Optimizations
In order to reduce power consumption, several system level optimizations are implemented in Explorer RPUs. These include:
- Fast shutdown ensuring longer sleep and shorter awake cycles
- Allowing the device to sleep between frames
- Allowing the internal Embedded Control Unit (ECU) to run autonomously so that the stack on the external MCU can remain asleep
- Implementing aggressive power gating when the device is not in use
- The native word size of the DSP engine (which we refer to as the Modulation and Coding Processor or MCP) is 12-bit/24-bit as opposed to a traditional 16-bit/32-bit DSP, resulting in direct power savings
The MCP and ECU provide the flexibility of an SDR: the ECU is C programmable and executes the control state machine while the MCP is a VLIW SIMD engine that comes with LTE specific library routines. The MCP and ECU provide the ability to quickly fix interoperability and field issues through firmware upgrades. Additionally a firmware based approach allows an easy upgrade to the evolving features in LTE Cat-0 and Cat-M standards.
To summarize, the Explorer Series5 RPU architecture provide a low-power, area-efficient and flexible engine to implement LTE Cat-0/1 for M2M and IoT applications. Although this discussion focuses primarily on the Explorer architecture which provides flexibility for evolving standards such as LTE for IoT, Imagination also offers the Ensigma Whisper IP family for IoT applications where extremely low power and area are critical.