There is no question about the potential that wearable technology has to take the semiconductor market into a thriving new era of growth. A lot of the innovative devices in wearables have predominantly been driven by chips based around processor IP technologies from Imagination: most smart glasses today use a PowerVR GPU, while a large number of smartwatches feature MIPS CPUs.

However, many wearables today use suboptimal solutions that compromise user experience and prevent widespread adoption. On the low end, wearables generally use multiple chips to achieve the functionality needed, leading to expensive, compromised solutions. Higher end smartwatches generally use retrofitted smartphone processors, leading to overpowered, overdesigned devices that require frequent recharging. For wearables to really take off with consumers, they need to provide the optimal balance of performance, ultra-low power and long lasting battery life.

Providing an answer to this problem has been the aim of Ineda Systems, a company founded by industry veterans who have recently been backed by a number of venture capital companies, including Samsung Catalyst Fund and Qualcomm Ventures in a high profile round of funding.

Ineda SystemsIneda Systems (pronounced “E-ne-da”) is a start-up company founded by industry veterans from the United States and India

Dhanush WPUs: a versatile product line designed for wearables and centered on MIPS

Ineda has recently announced the Dhanush family of Wearable Processor Units (WPUs™), the industry’s first wearable SoC designed to meet the stringent power and performance needs of the wearable and IoT markets. Designed from the ground-up, Ineda’s silicon is optimized for long battery life, along with the scalable performance that is required to run various applications in the wearable and IoT space. Ineda offers a range of low power, high performance SoCs designed to support a wide variety of devices, including fitness bands, smart watches, glasses, sports cameras and others.

The first available WPU is Dhanush Micro; it offers customers developing multi-function smartwatches class-leading performance and minimal power consumption. Dhanush Micro will deliver long lasting battery life and increased functionality such as more accurate location awareness and better sensor integration. This makes Dhanush Micro the ideal solution for device manufacturers looking to accelerate time to market and exceed end-user expectations.

Ineda Dhanush WPU - MicroDhanush Micro targets smartwatches and wrist bands

Ineda believes these solutions will bring together what is a very fragmented wearables market and drive it to its true potential; to find out more about the company’s platforms and how you they scale for various applications like voice recognition or 3D rendering, visit this link.

MIPS is the ideal CPU for wearable and IoT devices

MIPS is a highly scalable CPU architecture that spans applications from lightweight 32-bit embedded microcontrollers for industrial, automotive and IoT devices all the way up to high performance, industrial strength 64-bit multi-core processors for networking and communications infrastructure. For each of these applications, the MIPS architecture offers high performance, power efficiency and a highly compact silicon footprint, leading to a lower cost, more efficient design.

MIPS CPUs have proven to be the ideal choice for ultra-low power designs such as wearables. MIPS is a sophisticated yet cleaner, pure RISC architecture which achieves better performance at lower frequencies and in a smaller area compared to competing solutions. For embedded and microcontroller-type applications, MIPS CPUs offer industry-leading performance – up to 2.56x higher in DSP operations versus the competition.

 MIPS microAptiv v the competitionMIPS microAptiv CPUs achieve much better DSP performance at lower power

This is because we have kept the core architecture extremely compact with minimal frills but introduced a number of unique features such as improved co-processor support, advanced multithreading and hardware virtualization.

MIPS interAptiv v competitionMIPS interAptiv CPUs can use multi-threading to achieve superior performance in a range of applications, including web browsing, media playback or gaming

The MIPS instruction set architecture (ISA) offers a range of unique power saving instructions, enabling fine-grain control over all parts of the chip. All MIPS CPUs implement fine-grain clock gating to reduce dynamic power and voltage/frequency scaling to allow on-the-fly clock frequency changes. We are also developing our DOKs (Design Optimization Kits) and working with our EDA tools partners to help our MIPS licensees implement low-power design flows which deliver substantial silicon PPA gains while reducing design cycle times.

Collaborating on the world’s first Wearable Processing Unit

Ineda is an innovative partner and one of the first companies to truly understand market requirements and prepare for widespread adoption of wearables. By choosing off-the-shelf MIPS CPUs from Imagination, Ineda is able to build four high performance, low power designs that will be deployed in a number of embedded, wearables and IoT applications.

Do you own any wearable device? What do you think about Ineda’s solutions for wearables? If you have any questions, please leave a comment in the box below. For instant news about wearables, MIPS and Imagination, follow us on Twitter (@ImaginationPR, @MIPSGuru) and keep coming back to our blog.

Note: This article has been edited for clarity.

Comments

  • Angara Kumar

    Is this in production? I want to buy a smart watch, can you suggest the exact OEM or device part which i can buy having this?

    • Yes, like the article says, they are sampling and working with several partners right now. You should see products and more announcements (very) soon.

  • Angara Kumar

    Is this in production? I want to buy a smart watch, can you suggest the exact OEM or device part which i can buy having this?

    • Yes, like the article says, they are sampling and working with several partners right now. You should see products and more announcements (very) soon.

  • Tangey

    Without defining “the competition” the comparative DSP table means virtually nothing. One assumes the competition is arm, but which arm IP ?, A7, A9, A57, something else.

    It’s like arm doing a comparison with an anonymous “comparative” MIPS processor.

    One assumes such a ground-up soc design will be incorporarating radio functionality (Bluetooth/wifi) on chip, for maximum integration and power saving and power budget control.

    So does Ineda use IMG RPU ?

    • Our policy is to not name competitors directly. However, if you look closely, you will see that I have actually defined the competition.

      For microAptiv, I have put the class of the competing CPU: MCU. I am comparing against the highest-performance CPU IP core for microcontrollers available from the competition right now.

      For interAptiv, I have compared it against an apps processor already used in certain wearables and some low-end to mid-range smartphones/tablets (hint: it is very popular in a lot of quad-core affordable phones in Asia).

      The color should be self-explanatory when it comes to the name of the competitor.

      Care to take a more educated guess now?

      Regards,
      Alex.

    • Regarding the RPU, I can’t confirm or deny that. Ineda will disclose more about the connectivity part later.

    • Your question has been answered in our latest press release:

      New customers of Imagination’s Ensigma Wi-Fi/Bluetooth combo IP cores include Ineda, Toshiba, Toumaz and multiple fabless companies from Korea and China including Rockchip and others from around the world who will be announced publicly at a later time.

      https://www.imgtec.com/news/detail.asp?ID=877

      Regards,
      Alex.

      • tangey

        many thanks, I actually saw that literally a few moments before I came back to this blog.

  • Tangey

    Without defining “the competition” the comparative DSP table means virtually nothing. One assumes the competition is arm, but which arm IP ?, A7, A9, A57, something else.

    It’s like arm doing a comparison with an anonymous “comparative” MIPS processor.

    One assumes such a ground-up soc design will be incorporarating radio functionality (Bluetooth/wifi) on chip, for maximum integration and power saving and power budget control.

    So does Ineda use IMG RPU ?

    • Our policy is to not name competitors directly. However, if you look closely, you will see that I have actually defined the competition.

      For microAptiv, I have put the class of the competing CPU: MCU. I am comparing against the highest-performance CPU IP core for microcontrollers available from the competition right now.

      For interAptiv, I have compared it against an apps processor already used in certain wearables and some low-end to mid-range smartphones/tablets (hint: it is very popular in a lot of quad-core affordable phones in Asia).

      The color should be self-explanatory when it comes to the name of the competitor.

      Care to take a more educated guess now?

      Regards,
      Alex.

    • Regarding the RPU, I can’t confirm or deny that. Ineda will disclose more about the connectivity part later.

    • Your question has been answered in our latest press release:

      New customers of Imagination’s Ensigma Wi-Fi/Bluetooth combo IP cores include Ineda, Toshiba, Toumaz and multiple fabless companies from Korea and China including Rockchip and others from around the world who will be announced publicly at a later time.

      https://www.imgtec.com/news/detail.asp?ID=877

      Regards,
      Alex.

      • tangey

        many thanks, I actually saw that literally a few moments before I came back to this blog.

  • Kathy

    @Tangey,
    Going by the blog and the block diagram shown, my personal opinion RPU may be an add on chip on top of this WPU.

  • Kathy

    @Tangey,
    Going by the blog and the block diagram shown, my personal opinion RPU may be an add on chip on top of this WPU.