Two months ago I was returning home from our first ever Imagination Summit in Japan. While waiting to board the airplane that would take me back to England, I saw a billboard sign for Nissan – “WHAT IF_the world’s fastest man went even faster?”. That’s an interesting question, I said to myself.

A few weeks later a new email arrived in my inbox from my colleagues in the engineering team informing me that MIPS P5600 had entered the CoreMark chart straight at the top with a record-breaking score of 5.6 CoreMark/MHz per CPU.

The world’s fastest single-threaded CPU had gone even faster.

This increase in performance was no accident. Like Nissan, we have always been driven to beat the best, even when the best is ourselves; P5600 is now the new king of CoreMark, beating the previous top score held by our award-winning MIPS proAptiv processor.

The result has also been certified by EEMBC, the premier and long-standing embedded processor benchmarking consortium that designs and maintains CoreMark; you can find the complete list of certified results on their website.

To put this new result into perspective, a MIPS P5600 CPU delivers 20% more CoreMark/MHz performance than its direct competitor while being significantly smaller in area.


MIPS P5600 CPU - CoreMark per MHz performance MIPS P5600 offers 20% more raw performance in a smaller area

MIPS P5600 even scores higher in CoreMark/MHz than Intel’s desktop line of CPUs. For example, an Intel® Core™ i7-2640M processor achieves 14513.79 CoreMark at 2.8 GHz, or 5.18 CoreMark/MHz – nearly 10% lower than the latest result for MIPS P5600.

MIPS P5600 has the highest certified CoreMark/MHz score of all licensable CPUs.

This unprecedented level of performance efficiency will offer a welcome boost to MIPS-based embedded processors used for power-sensitive applications such as mobile, home entertainment, networking, automotive and many others.

Even more importantly, these outstanding results have been achieved using the latest off-the-shelf GCC compiler. All of our customers can access this high-performance toolchain either as source from partners or packaged in SDKs from Imagination. This approach is in contrast with some of our competitors that achieve their best benchmark scores with expensive, closed-source toolchains. Instead, Imagination is focused on building an open ecosystem that delivers performance quickly and painlessly, an important consideration for reducing time-to-market in mobile and embedded applications.

A quick recap of MIPS P5600

P5600 is a member of our MIPS Warrior P-class processor family and targets ultimate performance for mobile and embedded applications.

MIPS P5600 Series5 CPUMIPS P5600 features a powerful, feature-rich micro-architecture

P5600 is a 32-bit CPU based on Release 5 of the MIPS architecture and includes a series of unique features such as:

  • A fast 128-bit SIMD engine with over 150 integer and floating-point instructions for accelerating multimedia processing and other matrix-type operations
  • Full hardware virtualization supporting multiple fully isolated guest operating systems running in parallel.
  • Enhanced security for consumer and enterprise applications; this includes the ability to support multiple TEEs (Trusted Execution Environments) on a single CPU.
  • Best in class, advanced branch prediction mechanisms, page table walking hardware in TLB for optimal performance, instruction bonding for up to 2x increase on memory-intensive data movement routines
  • Enhanced Virtual Addressing (EVA) for more flexible usage of virtual address space, providing easy and efficient use of memory; eXtended Physical Addressing (XPA) support to fully utilize up to 1 Terabyte of memory (40-bits)

This high-end MIPS CPU is also part of our third generation of multi-issue, OoO (Out-of-Order), fully synthesizable processors; the figure below illustrates the evolution of high-performance MIPS CPUs over time, from 74K and proAptiv to present day.

MIPS P5600 - the evolution of MIPS P-class CPUsThe evolution of high-end 32-bit MIPS CPUs

MIPS P5600 features a series of improvements over previous generation proAptiv CPUs, including enhanced fetch efficiency, reduced L2 cache latency and pre-fetching; additionally, improvements in cache replay and memory disambiguation contribute to gains in performance for a wide variety of real world-applications (e.g. memcopy performance).

We are very proud of the record-breaking results in performance that the new MIPS Warrior CPUs continue to deliver. This achievement is built on a heritage of designing high-performance MIPS CPUs; advancements in instruction set architecture (e.g. Release 6) and memory subsystems together with continuous innovation in micro-architecture implementations will lead to even better results.

By combining MIPS Warrior CPUs, PowerVR multimedia IP and Ensigma connectivity IP, system engineers can design state of the art embedded processors that deliver best in class performance at lower power consumption and smaller area; you can read more about building highly competitive platforms using our hardware IP here[1] and here[2].

If you want to get the latest news and updates about MIPS, make sure to follow us on Twitter (@ImaginationPR, @MIPSGuru, @MIPSdev), Facebook and LinkedIn. For those interested in knowing more about CPU benchmarks, come back to our blog for an upcoming article detailing CoreMark, DMIPS and other industry benchmarks.

Categories: Networking Tags: CPU MIPS


  • Hossein

    Look forward to the P6400 64bit variant

  • Dave Hardt

    Airplane ? You mean aeroplane !!

  • Tangey


    That is a pretty impressive result. It of course means that you can run at lower Mhz and get the same performance as the competition. However, I guess in many of the markets you operate, Perf/watt is a more crucial metric than perf/Mhz. Little point, for example in being 20% faster at any given clock, if you burn 40% more power

    So for the graph above, and also for the Intel part, do you have comparative Perf/watt figures ?

  • gianni

    Why arent we seeing any maimstream devices adopting mips then?

  • Eponymous

    when we will see soc with P5600 ?

  • Marius Cirsta

    That’s nice but it would be nice to see it in a SOC and in an Android device. There’s also a need to tackle the binary ARM stuff in Android that need to be emulated by non-ARM SOCs.
    I know Google can do better in this respect ( like use intermediate code for binaries ) but it needs to be pushed in this direction by interested parties ( Intel on the X86 front and IMG on the MIPS side )