The launch of our brand new MIPS I6400 64-bit CPU marks the beginning of a fresh chapter for 64-bit MIPS processors. This article aims to offer you an introduction to the latest version of our MIPS64 architecture (one of the three 64-bit CPU architectures supported by Android 5.0 Lollipop) while answering a few of the questions that readers have been asking over the past month.
When was the first 64-bit MIPS CPU introduced?
Originally introduced in the early 1990s (a full decade before the first mainstream 64-bit x86 implementation), MIPS III was the first 64-bit version of the MIPS ISA (Instruction Set Architecture) and one of the earliest 64-bit RISC architectures.
In 1991, Toshiba, NEC, Integrated Device Technology, LSI Logic, Performance Semiconductor and Siemens AG announced they had licensed MIPS R4000, the world’s first 64-bit RISC CPU. Based on the 64-bit MIPS III architecture, R4000 was hugely popular in the workstation and server markets and enjoyed the privilege of being selected as the CPU of choice for the Advanced Computing Environment (ACE).
Since the launch of R4000, 64-bit MIPS CPUs have been integrated in configurations that scale from single core versions to tens of processors on a single chip, offering unprecedented throughput, power efficiency and programmability for many applications.
Where are MIPS64 CPUs used?
The architecture has seen a continued evolution over time which has helped our partners maintain leadership in their established markets but also enter and proliferate across new ones. 64-bit MIPS CPUs have shipped in hundreds of millions of devices, from game consoles and set-top boxes to ultra-high performance networking equipment.
For example, Nintendo 64 – one of the defining game consoles of the 1990s – used a 64-bit MIPS CPU.
Fun fact: One of the first games created for Nintendo 64 was Super Mario 64. During testing, the team of game developers created MIPS, a golden rabbit inspired by Alice’s Adventures in Wonderland and named after the application processor used in the Nintendo 64 game console.
MIPS proved to be so popular that he was included in the final version of the game – and in several remakes since then.
Recent examples of MIPS64-based SoCs for ultra-high performance networking, storage and other enterprise applications include the range of Broadcom XLP Series processors (XLP200, XLP500, and XLP900) and the Cavium OCTEON III family (CN70XX and CN71XX).
What is new for the MIPS64 architecture?
In an article published previously (The incredible evolution of the MIPS architecture), I described the rich heritage of 32- and 64-bit MIPS CPUs and covered how the architecture has adapted over time to meet and exceed industry requirements.
Now it is time to find out what’s new and where 64-bit computing is headed in the near future.
The most recent version of our architecture is called MIPS Release 6 and applies to both MIPS32 and MIPS64 families. Release 6 takes an already pure RISC ISA and further streamlines it for maximum performance and power efficiency; here is what we’ve added:
- The instruction set has been simplified and the opcode map has been improved for future expansion.
- A powerful family of compact branches with no delay slot: These include transfers with large 26- and 21-bit target address ranges, a full set of comparisons between registers and against zero and a full set of conditional branch and link instructions that compare to zero.
- Compact Indexed Jump instructions with no delay slot: Designed to support large absolute addresses.
- Instructions to generate large constants, loading (adding) constants to bits 16-31, 32-47, and 48-63.
- PC-relative instructions: In addition to branches and jumps, loads of 32- and 64-bit data and address generation with large relative offsets. Release 6 has true PC+offset relative-addressing control-transfer instructions that can span up to 26 bits (256MB), without the alignment restriction of the Jump (J) instruction (which can still be used in Release 6).
- Integer accumulator instructions and the HI/LO registers are removed from the Release 6 base instruction set and moved to the DSP Module.
- Bit-reversal and byte-alignment instructions migrated from DSP to Release 6 base instruction set.
- Multiply and Divide instructions are redefined to produce a single GPR result.
- Release 6 enhances support for the 32-register FPU mode and makes it the default in both MIPS32 and MIPS64, compared to the legacy 16-register FP mode. This is accompanied by full toolchain support and performance improvements.
- Release 6 is the first version of the MIPS ISA that updates FPU from IEEE-754-1985 to IEEE-754R-2008. This includes a variety of new instructions, most prominently the Fused Multiply Add instructions for HPC applications.
- Release 6 introduces advanced software prefetch instructions that can target L1, L2 or L3 cache levels. These can be used to optimize high-performance database, multimedia and scientific applications.
- Indexed addressing is superseded by scaled-addressing instructions favored by modern compilers
- Changes to 32 and 64-bit operation: StatusUX mode (32-bit signed address wrapping on a 64-bit machine, for the purpose of compatibility) now applied only to user-mode memory references. Release 6 extends this to apply to instruction fetch and to the new AUI instruction.
The MIPS I-class I6400 64-bit CPU we’ve announced at the start of September is the first core that implements the MIPS64 Release 6 architecture. I6400 includes a number of exciting features (simultaneous multi-threading, 128-bit SIMD, full hardware virtualization, advanced power management, etc.) designed to address current and future market requirements for mobile, home entertainment, automotive, networking and many other markets. Furthermore, MIPS64 is one of the three architectures supported in Android 5.0 Lollipop.
The diagram below shows how multi-threading MIPS CPUs evolved over time to form what is now the revolutionary Warrior I-class:
We are very excited about the performance and features included in this release. Customer engagements regarding 32- and 64-bit MIPS Warrior CPUs continue very positively, with a number of new agreements signed recently (including with a Tier 1 customer) and many more underway.
I hope this article has answered your questions about the new MIPS64 architecture. Make sure you follow us on Twitter (@ImaginationPR, @MIPSGuru) for more news and announcements from our MIPS ecosystem.