Although mainly known for our leadership position in CPU IP for digital home and networking, the MIPS architecture has recently seen rapid growth in the 32-bit microcontroller space thanks to the expanding list of silicon partners that are offering high-performance, feature-rich and low-power solutions at affordable price points.

The most recent example of our expansion into MCUs is the 200MHz 32-bit PIC32MZ family from Microchip. PIC32MZ MCUs integrate our microAptiv UP CPU IP core which enables Microchip to offer industry-leading performance at 330 DMIPS and 3.28 CoreMark™/MHz.

Microchip PIC32MZ block diagram - MIPS microAptivThe Microchip PIC32MZ MCU integrates a MIPS microAptiv CPU IP core

The PIC32MZ comes fully loaded with up to 2MB of Dual-Panel Flash with Live Update, 512KB SRAM and 16KB Instruction cache and 4KB data cache memories. This newest family in the PIC32 portfolio also offers a full suite of embedded connectivity options and peripherals, including 10/100 Ethernet MAC, Hi-Speed USB MAC/PHY (a first for PIC® MCUs), audio, graphics, crypto engine (supporting AES, 3DES, SHA) and dual CAN ports, all vital in supporting today’s complex applications.

By transitioning to the new MIPS microAptiv core, the PIC32MZ family offers a more than 3x increase in performance and better signal processing capabilities over the previous M4K-based PIC32MX families. In addition, the microAptiv core includes an Instruction Set Architecture (ISA) called microMIPS that reduces code size by up to 30% compared to executing 32-bit only code. This enables the PIC32MZ to load and execute application software in less memory.

Microchip_PIC32MZ - MIPS microAptiv)The PIC32MZ embedded connectivity MCU family is designed to address a wide range of application markets

The MIPS microAptiv family is available in two versions: microAptiv UC and microAptiv UP. microAptiv UC includes a SRAM controller interface and Memory Protection Unit designed for use in real-time, high performance low power microcontroller applications that are controlled by a Real Time OS (RTOS) or application-specific kernel. microAptiv UP contains a high performance cache controller and Memory Management Unit which enables it to be designed into Linux based systems.

MIPS microAptiv_UP_block_diagramA block diagram of the microAptiv UP CPU IP core inside PIC32MZ MCUs

Both microAptiv processor cores can run in MIPS32 mode, microMIPS only mode or combined.

The microAptiv cores contain many application-specific features including high performance, comprehensive DSP/SIMD functionality (more than 150 instructions are supported) that addresses control and signal processing requirements for a wide range of microcontroller and entry-level embedded segments.

Why choose MIPS32-based CPU IP for your MCUs?

MIPS-based MCUs are used in a wide and very diverse set of applications including industrial, office automation, automotive, consumer electronic systems and leading-edge technologies such as wireless communications. Furthermore, we’ve recently seen growing demand from the wearable and ultra-portable market; companies targeting these markets are looking to silicon IP providers like Imagination to deliver performance and power efficient solutions that can be easily integrated in fully-featured products.

CPU IP cores for microcontrollers need to be all-round flexible designs that are able to deliver higher levels of performance efficiency, improved real-time response, lower power and a broad tools and developer ecosystem. And the requirements continue to grow, especially with the new challenges presented by designing for the Internet of Things: better security, the ability to create more complex RTOS-controlled software and the ability to support a growing number of interfaces.

The microAptiv and future MIPS Series5 ‘Warrior’ M-class cores are perfectly positioned to provide an ideal 32-bit MCU solution for these next-generation applications. We understand that picking the right processor architecture is a key decision criterion to achieving performance, cost and time-to-market objectives in a MCU product. This is why we’ve made sure that the MIPS32 architecture enables our partners to design higher performance, lower power solutions with more advanced features and superior development support.

In the words of Jim Turley from his “Micro-Super-Computer-Chip‘ article inside the EE Journal: “With sub-$10 chips and sub-$150 computer boards, it looks like MIPS took over the world after all.”

We will be demonstrating the PIC32MZ on a Microchip multimedia board at the Embedded World 2014 event (February 25th – 27th) in in Nürnberg, Germany, so make sure you drop by our booth if you are attending the conference. In the meantime, follow us on Twitter (@ImaginationPR and @MIPSGuru) for the latest news and announcements from Imagination and its partners.


  • Fabián Rodrigo Romo Rivera

    A book about this new MCU is possible by Lucio Di Jasio?

  • Luiz Carlos

    Looking to block diagram of the PIC32MZ, the EBI peripheral is on the same BUS (System Bus) of the Data Ram Bank 1 and 2, assuming the the EBI is limited to the 50 MHZ acces speed, but can access 16MB (RAM), and we still have a SPI with 2GB SD card attached on other port.

    Will be possible to port Linux to this chip ?

    Best regards !

    • Hi,

      It is theoretically possible to run a flavor of Linux on this chip. For more details and tech support from Microchip, I would recommend you use their PIC32 forums for developers.


      • Luiz Carlos


        This forum is one of the best sources for MCHP stuff, even better than official information :), really top guys there, and even the guys of the are amazing…

        But the thing is, I asked to you because your intimacy with the core guts, especially when explains the microAptiv UC and UP difference, and Micromips code efficiency.

        The MX is a very new family, and MZ is whole new world, so to conclude, few people can undestand deeply in the architecture to answer this type of question, and good knowledge of linux too, therefore, I believe the hardest work would redirect the memory management to work with the EBI, almost like part of porting process.

        Thanks for reply !