The newly-announced MIPS M51xx (M5100 and M5150) processors are two important members of the Series5 Warrior family, the most exciting generation of CPUs in the recent history of MIPS. Both M5100 and M5150 are fully synthesizable CPU IP cores that focus on delivering leading performance efficiency and a unique feature set for the MCU and embedded markets.
Microcontrollers are a class of processors that are quickly making a comeback in technology circles, especially in the context of low-power wearables and “always on, always connected” Internet of Things (IoT) applications. Although consumers usually get excited about the high-end spectrum of CPU IP roadmaps, MCUs are a very important segment that enables most of the functionality in every device we use on a daily basis.
For example, there are many more CPUs in a smartphone other than the main application processor including gyro sensors, touch and display controllers, audio DSPs, connectivity modules – which all use one or more microcontrollers. This means that for every billion smartphones or tablets sold, there are several billions of these tiny processors ticking inside.
MCUs can also be found in a car’s engine control unit (ECU); the processor gathers data from dozens of other sensors and calculates the best spark and fuel injector timing. A modern ECU usually contains a 32-bit processor running at around 50 MHz, requires a few MBs of memory, and ensures lower emissions and better mileage.
Therefore designing optimal CPU IP for MCUs is one of the key elements to ensuring the long-term success and wide market applicability of MIPS processors.
The complete feature set of the MIPS M5100 and M5150 processors
When it was first introduced in 2012, microAptiv offered an incredibly powerful and flexible solution that delivered the ultimate best in class CPU performance and incorporated the low power principles of the MIPS32 architecture and microMIPS ISA.
Based on the valuable feedback gathered from deploying the market-leading microAptiv range to our customers, our engineering team has worked tirelessly to improve on what made microAptiv so amazing while incorporating the latest features in the MIPS Release 5 Architecture.
The new MIPS M5100 and M5150 CPUs share the same 5-pipeline design that sits at the core of microAptiv, while adding a few elements to the mix:
M5100 and M5150 are the only MCU-class CPU IP cores that feature hardware virtualization. This unique feature provides increased security and reliability for a wide range of applications. With virtualization, multiple, unmodified, operating systems and applications can run independently and securely at the same time on a single, trusted platform. Designers can take advantage of this to develop systems that provide a secure path to deliver updates/downloads, and benefit from enhanced IP protection.
A very useful example of how companies can use this feature is related to wearables. Once integrated into a wearable device, M5100 or M5150 could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another, under RTOS, can provide the audio and graphics capabilities.
– FPU (optional)
The FPU complies with single and double precision IEEE 754 standards and supports IEEE-754 2008 Nan and ABS instructions. The unit includes a dedicated 7-stage pipeline that operates in parallel with the core integer pipeline. Most instructions execute with 1 cycle throughput and 4 cycle latency, making it ideal for real-time applications that make extensive use of maths coprocessors.
– Ultra-secure debugging (optional)
The new M-class cores include anti-tamper features that provide an additional layer of security against potential external attacks. A secure debug feature prevents external debug probes from accessing the core internals so an application’s code stays safe and secure inside the core at all times.
Thanks to these characteristics, the MIPS M5100 and M5150 low-power processors greatly expand Imagination’s technology lead for MCUs, both in performance and feature set.
Flexible designs for the next wave of embedded computing
MIPS M5100 is designed to handle all MCU application-specific requirements and provides real-time performance. It is optimized for lower-cost, highly low-power MCUs where every square millimeter of area matters.
A block diagram of the MIPS M5100 CPU
MIPS M5150 incorporates a high performance L1 cache controller and virtual memory management support. The memory management unit enables it to power high-performance embedded systems that can execute operating systems with virtual memory support such as Linux.
A block diagram of the MIPS M5150 CPU
Finally, the two processors include the same powerful DSP engine that was present inside microAptiv, while our innovative microMIPS ISA is there to provide up to 30% code compression for applications where memory size is critical.
On the ecosystem side, a broad range of development tools are available for the M5100 and M5150 cores, from Imagination and partners, with additional support in development. This incudes compilers from Mentor Graphics and Green Hills, debuggers, simulators from Imperas, development boards plus Linux and RTOSes, including Imagination’s MeOs.
A snapshot of the MIPS M51xx ecosystem
In addition, several hypervisors are available/under development including open source KVM and a microkernel version from Imagination, and others from third party hypervisor developers.
What do you think about virtualization in MCUs? Let us know in the comment box below and keep coming back to our blog to find out more about our MIPS Series5 ‘Warrior’ CPUs. Follow us on Twitter (@ImaginationPR and @MIPSGuru) for the latest news and announcements from Imagination, our partners and licensees.