In a press release issued today PEZY Computing announced it is working on a MIPS64-based PEZY-SC2 family of many-core chips for supercomputers and HPC applications that will scale up to 4096 processing nodes. The 64-bit MIPS CPUs will act as the host processors for the system, making PEZY-SC2 the first generation of 64-bit HPC processors from the Japanese company.

PEZY is a fabless startup focusing on compute-intensive, highly parallel applications. The company already occupies the top three spots on the Green500 list of energy-efficient HPC makers, setting a world record with the Shoubo supercomputer that consumes only 7W per GFLOPS.

PEZY ComputingShoubu is the first and only supercomputer on the Green500 list to surpass seven GFLOPS/watt milestone

Founder and CEO Motoaki Saito named PEZY by combining the initials of four decimal unit prefixes: peta, exa, zeta and yotta. For reference, 1 petaFLOPS represents one thousand teraFLOPS (i.e. 1,000 trillion); exa, zetta and yotta are 1000 times the value of the former unit, respectively.

Dr. Saito has an encyclopedic knowledge of technology and is a maverick entrepreneur, having established several companies that focus on various aspects of advanced computing and related technologies. For example, one of his first enterprises out of university manufactured more than 8,000 high-end medical systems which were developed in-house to large hospitals worldwide.

PEZY Computing is an exciting addition to the growing family of partners that value the higher performance and greater energy efficiency delivered by the MIPS architecture. I am very eager to see the new PEZY-SC2 many-core processors achieve new breakthroughs in green supercomputing.

MIPS and supercomputers

MIPS has a rich history in HPC applications. Initially used in multiple SGI workstations and desktop computers in the late 1990s and early 2000s, 64-bit MIPS CPUs were later deployed inside several high-profile supercomputers.

One example is the Cenju-4 parallel machine designed by NEC Corp. Delivering 400 GFLOPS of performance, Cenju-4 integrated up to 1024 MIPS R10000 CPUs bound by a multistage network fabric that had multicast synchronization functions.

SiCortex SC5832 was another MIPS64-based supercomputer consisting of 5,832 processors and achieving 5.8 TFLOPS of peak performance. Complete with its 8 TB of system memory, the SC5832 was able to fit in a single cabinet and required less than 20 kW of power to run at full throttle.

SiCortex SC5832 - MIPS64SiCortex-based supercomputers had up to 36 motherboards, each of which had 162 processors

Today, high-performance MIPS CPUs can be found in many networking, embedded and desktop SoCs from Cavium, Broadcom, Baikal Electronics and Loongson Technology.

The MIPS architecture provides many great features for HPC applications, including hardware multithreading (up to four threads per CPU), 128-bit SIMD, and full hardware virtualization (up to 255 guest operating systems). For example, hardware multithreading is very important since many-core chips prefer to use in-order execution cores and rely on multithreading to avoid stalling.

SoC designers can integrate up to 64 clusters of hexacore MIPS I6400 CPUs, each having up to four threads respectively. The diagram below presents how the 64-bit I6400 CPU can easily scale to address the requirements of multiple markets:

MIPS I6400 - scalabilityThreads, cores and clusters – MIPS I6400 has them all!

For system architects looking to integrate Out-of-Order 64-bit processors, the recently released MIPS P6600 provides an ideal solution. A high-performance tuned implementation of our Release 6 architecture, MIPS P6600 also includes best-in-class branch prediction and our load/store instruction bonding mechanism, two technologies that provide a real boost in single-threaded workloads while keeping silicon area and power consumption in check.

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  • Alan

    The scalability of MIPS is impressive. I am waiting for CI40.

    Why CPU has 6 cores not 8 cores ? Symmetry in hardware always fires right signals – 1, 2, 4, 8, 16 .. was that a business or engineering decision.

    • Arthur Bugorski

      Often they make 8 cores physically but one or two or three cores will contain a manufacturing defect. If it’s one or two, then they disable the broken cores and still sell the chip whereas if they promised all 8 they’d have to scrap more cores raising the cost per unit.

      And yes, sometimes companies will disable two cores anyway if all 8 turn out perfect.

      I don’t know the specifics here, but this is a known industry practice.

      • I think what you’re referring to is binning which has little to do with what we’re doing here. We don’t manufacture chipsets so there is nothing to disable. We’re offering instead a way for companies to differentiate by introducing single-cluster, hexacore configurations.

    • The number of cores in cluster is not linked to symmetry, but to real-world use cases. The feedback we’re getting from customers is that there are applications where a hexacore cluster would be useful rather than a 2+4 dual-cluster configuration.

  • muser

    Will there be finally MIPS64 dev. board (as Ci20) with USB3, GEth, 802.11ac?