Prototyping a PowerVR Series6XT GPU using an optimized flow from Synopsys

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Andy Jolley is senior staff application consultant – worldwide product line lead, FPGA-based prototyping at Synopsys. Andy has been working with FPGA technologies for over 25 years and has been recently supporting customers with their complex CPU SoC and GPU IP prototyping needs on the Synopsys HAPS platforms while also providing support for worldwide engagements to deploy the same SoC and GPU IPs embedded into user applications.

PowerVR Rogue GPUs are built on market-leading efficiency principles that deliver a significant boost in performance over the previous generations of graphics processors. In order to achieve this high level of performance, GPU architectures harness significant parallel processing power to perform the most demanding graphics and compute tasks.

When configuring GPU IP for high performance, design teams face multiple challenges when trying to fit complex, high gate-count designs into the limited space of a single FPGA. Given the scalability of the Series6, Series6XE and Series6XT families (from half- to eight clusters), Imagination’s design team was faced by additional challenges when attempting to test these complex devices.

PowerVR Series6XT GPUPowerVR Series6XT GPUs scale from two to eight clusters

Since the alternative (i.e. fabricating test chips) has become an increasingly expensive and time-consuming process, Synopsys and Imagination worked together to build a more robust FPGA-based prototyping infrastructure.

The result is a new optimized flow that uses multiple FPGAs to model even the largest PowerVR GPUs; read on to find out how we were able to achieve this impressive result.

GPU prototyping requirements

The first step involved Synopsys starting on a proof-of-concept project which would demonstrate an FPGA-based prototype for Imagination’s PowerVR Series6 GPUs. The prototyping environment included a top-level test infrastructure for standalone regression tests.

This test infrastructure connected to a PC host via a PCIe port and stored test stimuli and results using a DDR3 memory interface. This enabled the test team to control and analyze the GPU, including the ability to configure the system through a Universal Multi-Resource BUS (UMRBus) and access the test and results data from the PC host.

 Synopsys - Top-level test infrastructure to support regression testsTop-level test infrastructure to support regression tests

The team manually partitioned the design for implementation on a Synopsys HAPS-70 S48 prototyping system comprising multiple FPGAs that achieved a clock speed of several MHz. 7,000 regression tests were then run on this system – all without the need to implement a test chip.

Not only did we partition a derivative design (an even larger device than the Series6 GPU), but also created additional test logic and sufficient performance to enable live video output. This was done using ProtoCompiler, a second generation of automated FPGA partitioning tools from Synopsys.

ProtoCompiler is designed to minimize the effort and time required to bring-up and then deploy a Synopsys HAPS series system for IP validation and software development. It incorporates automation features for design planning, logic synthesis, debug, and connectivity to other verification environments like Synopsys VCS and ZeBu. The prototyping software is tightly integrated with the HAPS series to deliver system performance.

The results and conclusion

The collaboration between Imagination and Synopsys showed how, given the right environment, design teams can use FPGAs to support early prototyping of the largest and most complex GPUs.

The success of both the PowerVR Series6 and Series6XT prototypes will mean that the Imagination design team is less dependent on the use of test chips to bring new GPUs to market. Early access to physical prototypes enables system validation, earlier software development and eases hardware-software integration.

Synopsys - PowerVR Series6 on HAPS-70A PowerVR Series6 GPU on the Synopsys HAPS-70

The final 12 MHz performance achieved with the prototyping platform helped Imagination to execute thousands of tests in a matter of hours and provided a platform for early software development. In addition, supporting the video output from the HAPS system allowed the use of real-time, real-world I/O to enable inspection of the correctness and quality of the image processing.

For more details on how we built the whole infrastructure and partitioned the design to fit on multiple FPGAs, please download this whitepaper.

The ability to accelerate the time to first prototype assists Imagination in bringing new products to market, and also helps Synopsys’ and Imagination’s mutual customers when they integrate Imagination GPUs into their SoCs.

For more news and announcements on PowerVR, follow us on Twitter (@ImaginationTech, @PowerVRInsider) and keep coming back to the blog.

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