MIPS is the shining star of the highly efficient, low power CPU design principles that have shaped the mobile and embedded industry for nearly three decades. In this article, I will try to offer you a quick overview of how the MIPS architecture evolved from its early beginnings in the Stanford University computer science labs to the present day.
The video below goes back to the roots of MIPS and shows how the architecture evolved over time; read on after the break to find out about the major milestones that have defined our processor technology.
It all started in the 1980s when a group of Stanford University researchers that included John L. Hennessy decided to create a new Instruction Set Architecture (ISA) for CPUs that would be based on achieving the best efficiency (i.e. performance as a function of area and power) in the industry.
Soon after, they founded MIPS Computer Systems, Inc. and released the first commercially-available microprocessor architectures: MIPS I and MIPS II. The MIPS ISA rapidly became the beacon for RISC, a principle of designing CPUs that emphasizes the importance of a compact instruction set to provide higher performance at lower power and reduced area.
Many of the original MIPS implementations were targeted at computer-like applications such as workstations and servers. In recent years, MIPS CPUs have largely been shipping in embedded applications, including mobile, wearables, home entertainment, networking, IoT and others.
Enter the first 64-bit MIPS ISA
Launched in 1991, the MIPS III ISA was the first to add 64-bit integers and addresses. The MIPS IV and MIPS V ISAs added improved floating-point operations and a new set of instructions that improved the efficiency of generated code and of data movement.
To this day, the MIPS32 and MIPS64 architectures provide a substantial performance, power and area advantage over competing microprocessor architectures. These advantages come as a result of improvements made in several contiguous disciplines: microarchitectural enhancements, better integration at the system level, the rapid proliferation of lower process nodes in mobile, and the amazing evolution of operating systems and compiler design.
The MIPS32 architecture is based on the MIPS II ISA, adding selected instructions from MIPS III, MIPS IV, and MIPS V to improve the efficiency of generated code and of data movement.
The MIPS64 architecture is based on the MIPS V ISA and is backward compatible with the MIPS32 architecture. Additionally, throughout the evolution of both architectures, each new MIPS ISA has been backward-compatible with previous ISAs.
Both the MIPS32 and MIPS64 architectures are intended to address the need for high-performance and low power for a wide range of cost-sensitive applications.
The advantages of the MIPS architecture
System designers opting for MIPS get a very flexible architecture that can support a wide range of operating systems and other kernel software. On top of that, MIPS32 and MIPS64 include provisions for adding optional components: modules of the base architecture, MIPS Application Specific Extensions (ASEs), User Defined Instructions (UDIs), and custom coprocessors to address the specific needs of particular markets. These components enable silicon vendors to implement specific functionality and tune their designs based on various efficiency goals and market requirements.
The flexibility and ease of programming for the MIPS architecture has enabled a vibrant ecosystem of partners that have built a complete tools and software chain around the hardware IP. Additionally, MIPS CPUs are the perfect processors to run Android, different Linux distributions and many real-time operating systems (RTOSes). For example, Google has recently announced MIPS64 is one of the three architectures supported by Android L. This version of the operating system enables ART – a new Android runtime which improves app performance – to run on MIPS CPUs.
The evolution of CPU architectures is a dynamic process that takes into account both the need to provide a stable platform for implementations, as well as new market and application areas that demand new capabilities. These enhancements are appropriate when they:
- are applicable to a wide market
- provide long-term benefit
- maintain architectural scalability
- are standardized to prevent fragmentation
- are a superset of the existing architecture
For more information on MIPS, visit our product pages at www.imgtec.com/mips. If you are a developer, check out the multitude of available resources and training material offered for free on our community website at community.imgtec.com/developers/mips.
Make sure you join us next time when we take a look at MIPS64 Release 6, our state of the art 64-bit MIPS architecture that is now supported in Android L. For more news and updates, follow us on Twitter (@ImaginationPR, @MIPSGuru), LinkedIn, Facebook and Google+.