New white paper from TIRIAS Research on the world of connected devices

TIRIAS Research is a high-tech research and advisory firm consisting of a team of experienced analysts which includes Jim McGregor and Kevin Krewell. We’ve recently asked them to take a look at our newly-announced MIPS I6400 64-bit CPU and offer their impressions and thoughts on this revolutionary design in the context of today’s fast-moving computing market.

New challenges in a connected world

The result of this collaboration has been a white paper which you can access for free here. In it, the authors identify the emergence of a new class of concepts (streaming media, cloud services, IoT, SDN, NFV, Big Data) that are linked primarily to the growing number of connected devices available worldwide.

Classes of IoT DevicesThere are several classes of IoT devices

The article starts off by looking at the new uses and business models around the collection and use of information. The way companies will collect and use data will determine the patterns driving IoT adoption, from simple sensors to the most advanced supercomputers and from electromechanical systems to humans. Given the wide breadth and applicability of these IoT platforms, forecasts for the connected devices or nodes can reach into the hundreds of billions:

Forecasts for Connected DevicesSource Nodes in 2020Forecasts for connected devices and source nodes in 2020

The authors then highlight some of the issues facing the electronics industry in the short- and long-term. They conclude that the rapid shift to a connected world has deep implications for hardware and software providers alike so building singular platforms for every application is neither practical nor feasible. Instead, semiconductor providers need to adopt a long-term strategy that goes beyond next generation devices and looks at building forward-looking scalable solutions and complete ecosystems.

Varying Performance Requirements for Smart GatewaysVarying performance requirements for smart gateways

These solutions require greater security, flexibility in performance, power and area, and smart reuse of hardware and software resources. The white paper explores these key areas in great detail, offering in-depth insights for each section.

MIPS I6400 offers scalability, security and best-in-class performance

The authors then drill down into the specifics of the MIPS architecture and describe how the MIPS Warrior CPU family meets the above requirements, offering integrated security and virtualization, the ability to scale from sensors through to high-performance computing, and full code compatibility across the range.

MIPS-Portfolio-and-Roadmap-15_10_14MIPS offers an industry-leading, comprehensive CPU IP roadmap covering any IoT requirements

For companies looking to build ultra-efficient computing platforms for mobile and embedded markets, MIPS I-class CPUs provide unmatched flexibility, supporting both 32-bit and 64-bit applications. Furthermore, SoC designers have access to multiple configuration options within the CPU cores (1-4 threads per CPU), in the number of CPU cores (2-6 cores per cluster), and the combination of clusters of CPU cores (1-64 clusters per SoC).

This level of multi-tiered scalability delivers one of the industry’s most power efficient CPU architectures and a platform capable of supporting the widest range of applications ever targeted by a MIPS CPU. MIPS I6400 also offers tangible benefits for the future of heterogeneous computing, being built for the ground up for integration in true heterogeneous platforms.

MIPS I6400 CPU - SoC using Imagination_IP_finalNext-generation heterogeneous processors for IoT devices can mix and match any of our MIPS, PowerVR and Ensigma silicon IP

In summary, the white paper offers a comprehensive look at the landscape of connected devices and the specific requirements of different computing gateways. It also provides a very good summary of how Imagination is addressing the challenges introduced by these connected devices by offering a complete range of processor IP that can target multiple markets more efficiently.

Make sure you download the full white paper and tell us what you think. For more news and updates, follow us on Twitter (@ImaginationPR, @MIPSGuru), LinkedIn, Facebook and Google+.

  • Alex, something ‘clicked’ with me today which now seems far more important than when I first read about the I-6400. The I-6400 allows for some serious customization to the customer does it not? Each core within a cluster could potentially have different L1, L2 cache sizes, No. of threads, SIMD engine or not, and of course clock speed… I’m sure there are more options.
    So for instance I am guessing that a customer could have 1 cluster of 6 cores, each core containing large L1 and L2 caches, SIMD engine, 2 threads per core, high clock speed. And then a 2nd cluster of 6 cores each core containing smaller L1 and L2 caches, no SIMD engine, only 1 thread per core, and low clock speed? Would this in theory be possible with the I-6400?
    I’m thinking in particular if say a customer wanted to produce an SoC with 12 cores, where you have 1 cluster of big cpu’s and another cluster of LITTLE cpu’s. 🙂

      • That’s a bit vague Alex but thanks for your reply none the less. I think I was hoping for a slightly more detailed answer considering that, I would say customization has got to be something that as an IP company you can champion as a big advantage over say the likes of Intel for example. I mean could Intel offer many many CPU configurations to suit the customers needs exactly… I think not, only if Intel could guarantee a substantial market for each configuration they manufactured… You (IMG) do not have that problem.

  • Alex, something ‘clicked’ with me today which now seems far more important than when I first read about the I-6400. The I-6400 allows for some serious customization to the customer does it not? Each core within a cluster could potentially have different L1, L2 cache sizes, No. of threads, SIMD engine or not, and of course clock speed… I’m sure there are more options.
    So for instance I am guessing that a customer could have 1 cluster of 6 cores, each core containing large L1 and L2 caches, SIMD engine, 2 threads per core, high clock speed. And then a 2nd cluster of 6 cores each core containing smaller L1 and L2 caches, no SIMD engine, only 1 thread per core, and low clock speed? Would this in theory be possible with the I-6400?
    I’m thinking in particular if say a customer wanted to produce an SoC with 12 cores, where you have 1 cluster of big cpu’s and another cluster of LITTLE cpu’s. 🙂

      • That’s a bit vague Alex but thanks for your reply none the less. I think I was hoping for a slightly more detailed answer considering that, I would say customization has got to be something that as an IP company you can champion as a big advantage over say the likes of Intel for example. I mean could Intel offer many many CPU configurations to suit the customers needs exactly… I think not, only if Intel could guarantee a substantial market for each configuration they manufactured… You (IMG) do not have that problem.

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