Designed for safety-critical systems in an autonomous age
MIPS I6500-F CPU IP: represents a new class of MIPS processors designed to ‘FortifAI’ next-generation intelligent systems – delivering scalable computing and extremely high system efficiency, and raising the bar on functional safety.
Ultimate system efficiency and scalability for multi-core heterogeneous designs
Heterogeneous computing will enable the dynamic scaling and sharing of on-demand compute power for next-generation intelligent systems. The I6500-F provides a high-performance, highly efficient backbone for many-core designs, scaling to 64 heterogeneous clusters of multi-threaded multi-core MIPS CPUs and other accelerators in a system.
Featuring rigorous QMS processes and safety methodology for addressing systematic and random failures, and with optimized safety measures to meet system level safety requirements, the MIPS I6500-F is designed to meet requirements for ASIL B(D) level, allowing it to target demanding automotive applications up to ASIL D, and is assessed by an independent safety assessor for formal compliance to ISO 26262 and IEC 61508 standards. It has been developed as a ‘Safety Element out of Context’ (SEooC) – a standard design that can be used across a range of applications.
The MIPS I6500-F provides a highly scalable foundation for building the many-core designs needed to handle the compute-intensive tasks in emerging safety-critical systems such as autonomous vehicles, industrial IoT and robotics. It scales to 64 heterogeneous clusters of multi-threaded multi-core MIPS CPUs, and through the MIPS Coherence Manager with AMBA® ACE interface, enables integration with heterogeneous CPU clusters and other accelerators at the SoC level.
Unique, powerful features
Hardware virtualization (VZ) lets designers save costs by safely and securely consolidating processes that might have run on multiple CPU cores in the past onto a single core today. Simultaneous Multi-threading (SMT) capability maximises instruction throughput, leading to higher CPU utilization and efficiency. The combination of SMT and VZ enables “zero context switching” for applications requiring real-time response. The MIPS I6500-F is also OmniShield-ready™, providing a strong foundation for security-by-separation.
High-performance functional safety for autonomous vehicles
The MIPS I6500-F core is stringently assessed and validated against ISO 26262 ASIL-B(D) for automotive. It will act as the central computer for sensor fusion in Fully Autonomous Driving (FAD) vehicles starting 2020.
MIPS I6500-F to be at the heart of Mobileye’s next-gen EyeQ®5 SoC for autonomous vehicles
Since EyeQ®2 (launched back in 2006) Mobileye has chosen MIPS CPUs to be at the heart of its ADAS camera solutions. By leveraging unique MIPS multi-threaded technology to efficiently control its image processing blocks, it has achieved a level of instructions per clock that approaches that of a fully accelerated solution. With the EyeQ®5, Mobileye is once again endorsing the MIPS architecture as the best approach for delivering camera-based automotive safety systems to ensure its technologies continue to prevent collisions and save lives.
Providing the performance needed for a new generation of safety-critical intelligent systems
Applications such as autonomous vehicles and industrial control systems in smart factories require ever-increasing levels of processing – exceeding the capabilities of other FuSa (Functional Safety) compliant CPU IP cores. With the extended performance capability of the I6500-F you can efficiently integrate increased intelligence – including AI techniques such as CNNs and DNNs – in your safety-critical device.
Delivering high-performance functional safety to the autonomous market
MIPS I6500-F core is ideal for safety-critical systems in industrial environments and is designed to be IEC 61508 certified for the most demanding industrial control applications.