Imagination Technologies Group plc (LSE: IMG, “Imagination”, “the Group”), a leading multimedia, communications and processor technology company, has launched the highly-efficient MIPS I-class I6400 CPU family.
This is a key strategic development for the Group as this 64-bit MIPS Warrior core is the first IP core to combine a 64-bit architecture and hardware virtualization with scalable performance through multi-threading, multi-core and multi-cluster coherent processing.
MIPS Warrior I-class processor cores set a new standard for mainstream 64-bit processing in applications including embedded, mobile, digital consumer, advanced communications, networking and storage – the broadest set of applications ever addressed by a single MIPS core family.
Its extraordinary feature set and performance/power/area leadership will enable customers to implement a smaller core at the same performance, or a faster core, in the same area.
Sir Hossein Yassaie, Chief Executive, commented:
“This is the MIPS Warrior core that the industry has been waiting for. Customers can now choose a CPU based on its technical superiority.
“This new product is more efficient, flexible and scalable than the competition and its feature set clearly lends itself to the needs of a wide range of next-generation applications including smartphones and tablets.
“We know that unique features like multi-threading provide significant advantages for many applications. We have already secured licensees for this new product across multiple markets.
“The Group is now able to provide MIPS IP cores for everything from microcontrollers to 64-bit servers, delivering choice across the range and changing the competitive dynamic in the industry.”
Imagination Technologies Group plc Tel: 020 7457 2020 (today) / 01923 260 511 (thereafter)
Sir Hossein Yassaie, CEO
Richard Smith, CFO
Instinctif Partners Tel: 020 7457 2020
Adrian Duffield / Kay Larsen
Note to editors
Inside the I6400 family of cores
· Highly efficient, scalable 64-bit performance: The I6400 will enable customers to set new price/performance points across markets. It achieves over 50% higher CoreMark performance and 30% higher DMIPS compared to leading competitors in its class*. The I6400 can be implemented across a very wide range of performance, power and area operating points and achieves high frequencies in aggressive implementations.
· Hardware multi-threading: The I6400 features hardware multi-threading technology that supports up to four hardware threads per core. Imagination’s proven MIPS multi-threading technology leads to higher utilization and CPU efficiency. The simultaneous multi-threading (SMT) technology in the I6400, which builds on the decades of combined multi-threading expertise in the MIPS and Imagination engineering teams, enables execution of multiple instructions from multiple threads every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% on popular industry benchmarks including SPECint and EEMBC’s CoreMark, with less than a 10% cluster area increase. Real-world applications such as browsers can also take significant advantage of multi-threading.
· Hardware virtualization: The I6400 joins the entire range of MIPS Warrior cores in incorporating hardware virtualization technology, providing increased security and reliability, and enabling a unified security and virtualization strategy throughout the system and across the entire SoC. As implemented in the I6400, this includes support for up to 15 secure/non-secure guests.
· Next-generation security: As part of Imagination’s unified security strategy, designed to address the privacy and security needs of evolving and emerging connected applications, the I6400 core is optimized to support multiple independent security contexts and multiple independent execution domains. This much enhanced security capability leverages technology from Imagination and its ecosystem partners and can encompass other critical components of an SoC. The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
· Advanced power management: With PowerGearing™ for MIPS, the I6400 features advanced power management capabilities. This includes the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
· Efficient FPU: The proven hardware Floating Point Unit (FPU) in the I6400 supports both single and double precision capabilities relevant to general computing as well as improved control systems processing.
· 128-bit SIMD: The I6400 features 128-bit SIMD support, delivering high performance and high throughput for a wide range of tasks that can exploit the efficiencies of SIMD execution in data-parallel applications. It is built on the MIPS SIMD architecture which adheres to true RISC philosophy, with instructions defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, as well as leverage of existing code. The SIMD in the I6400 supports a wide variety of integer (8, 16, 32 and 64-bit) and floating point (32, 64-bit) data types, making it highly efficient for many applications across audio, video, vision, and other computationally-intensive use cases.
Next-generation multicore coherency
The I6400 features the latest generation of the MIPS Coherency Manager fabric based on a new multicore coherent interconnect architecture. It supports multicore configurations of up to six cores per cluster where multiple cores on a single cluster can have different synthesis targets, and operate at different clock frequencies and voltages. The Coherency Manager fabric implements numerous high-performance features including hardware pre-fetching as well as wider buses and lower latencies compared to previous generations.
Scalable, multi-cluster coherency
I6400 cores are designed to be delivered in diverse combinations of threads, cores and clusters, supporting multi-cluster fabric configurations up to 64 clusters. The cores are also designed to operate in heterogeneous clusters in future SoC implementations leveraging CPUs, GPUs and other processing elements.
MIPS: the ultimate 64/32-bit architecture
Broad ecosystem of support
I6400 customers benefit from the broad ecosystem that already exists around MIPS, including software, tools and applications and the new prpl open source foundation. With founders Broadcom, Cavium, Ikanos, Ineda Systems, Ingenic Semiconductor, Lantiq, PMC, Qualcomm Incorporated and others, prpl is delivering exciting open source software for MIPS I-class and other Warrior cores with a focus on markets from IoT to datacenter.
Tools and software
A broad range of development tools and software is already available or in development for the I6400 cores, from Imagination and numerous companies across the MIPS ecosystem. In addition, the I6400 is optimized for the latest 64-bit and 32-bit mobile operating systems. The forthcoming ‘L’ release of Android includes support for 64-bit MIPS, building on long-time existing support for the 32-bit MIPS architecture. Hypervisors in development for the I-class cores will enable customers to take full advantage of hardware virtualization and enhanced multi-context security capabilities.
Getting started with the I6400 core
One of the first projects completed through the prpl open source foundation is support for the MIPS64 r6 architecture in the QEMU open source emulator, currently available at http://github.com/prplfoundation. With QEMU, developers can get started on developing applications and software for the 64-bit I6400. More information on the QEMU working group in prpl can be found at http://wiki.prplfoundation.org/wiki/QEMU.
Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014. Contact firstname.lastname@example.org for more information.
* Imagination benchmark results are preliminary; competitive results are based publicly available information.
About MIPS Processors
Imagination’s family of MIPS CPU IP cores are ideal for products where ultra-low power, compact silicon area and high levels of integration are required. The comprehensive portfolio of MIPS processor IP cores range from the smallest cores for 32-bit MCUs to high-performance 32-bit and 64-bit multi-core solutions. Based on a heritage of continuous innovations over more than three decades, including full support for 64-bit for more than 20 years, Imagination’s MIPS architecture is the industry’s most mature and efficient RISC architecture, delivering the highest performance and lowest power consumption in a given silicon area.
prpl (pronounced “Purple”) is an open-source, community-driven, collaborative, non-profit foundation targeting and supporting the MIPS architecture—and open to others—with a focus on enabling next-generation datacenter-to-device portable software and virtualized architectures. prpl represents leaders in the technology industry investing in innovation in efficiency, portability and compatibility for the good of a broad community of developers, businesses and consumers. Initial domains targeted by prpl include datacenter, networking & storage, connected consumer and embedded/IoT. See: www.prplfoundation.org.
About Imagination Technologies
Imagination is a global technology leader whose products touch the lives of billions of people across the globe. The company’s broad range of silicon IP (intellectual property) includes the key processing blocks needed to create the SoCs (Systems on Chips) that power all mobile, consumer and embedded electronics. Its unique software IP, infrastructure technologies and system solutions enable its customers get to market quickly with complete and highly differentiated SoC platforms. Imagination’s licensees include many of the world’s leading semiconductor manufacturers, network operators and OEMs/ODMs who are creating some of the world’s most iconic products. See: www.imgtec.com.
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