Tokyo, Japan: Imagination
Technologies, a leading multimedia chip technologies company, announces the
full roadmap for its Series2 generation of META processors, designed for the
SoC-centric (System-on-Chip) age of silicon design.
The META family of 32-bit SoC processor IP
cores is a unique range of embedded processors that combine both general
purpose and DSP capabilities within a hardware multi-threaded execution
infrastructure to deliver exceptionally high processor utilisation and
tolerance to SoC system latencies while also delivering new levels of real-time
response that makes them ideal for SoC applications.
Indeed, the META processors are able to
deliver both “”hard real time”” capabilities – the ability to respond to an
external event in a single clock cycle including complete context switch –
while also providing excellent Linux or Android applications processor
platforms with fully coherent caches and MMUs. The META family stands out as a
leading example of next generation SoC embedded processor architecture.
Furthermore, by the addition of features to
facilitate highly efficient integration with multi-standard communications
engines such as Imagination’s ENSIGMA UCC programmable Wi-Fi and demodulation
engines, META delivers a new generation of processors fully optimised for the
internet and broadcast connected world.
SoCs being designed today place very
different demands on embedded processors than those of a few years ago, as
levels of systems integration continue to rise and applications make increasing
use of high level APIs and operating systems. No longer is a single processor
the highest priority user of system resources – it must increasingly share bus
bandwidth, memory and other system resources with other sub-system processors
for multimedia, communications and other specialised functions. This means the
underlying architecture of embedded processors must be updated to reflect the
fundamental changes in operating environment. It is with this evolving
understanding of the practical realities of embedded processing in today’s SoCs
that Imagination has created the Series2 architecture for its META family of
Says Tony King-Smith, VP marketing,
Imagination: “”For too long chip designers have stuck to traditional concepts of
CPU-based SoC design, which is increasingly not appropriate for the levels of
system integration we’re now seeing in SoCs. Embedded processors – whether
running applications under Linux or highly optimised DSP algorithms – now need
to be much more effective in ensuring every clock cycle counts to minimise
power and maximise performance, Based on our years of experience of embedding
META processors in many of our SoC IP cores and customer SoC designs, as well
as our work with many of the world’s most advanced SoC vendors integrating our
high performance multimedia and communications engines with every major CPU
architecture, we’ve built on the core strengths of our unique META processor
architecture to meet the needs of SoCs far better than traditional CPUs for
today’s low power, high performance connected multimedia age.””
There are now three META processor product
· META HTP SoC Application Processors are designed to be a comprehensive
alternative to traditional multi-processor approaches, where high-level
operating systems (OS) are essential for application execution, alongside lower
level tasks with tough real time constraints and demanding DSP capabilities
· META MTP SoC Embedded Processors target applications such as high speed communications
and DSP intensive algorithms like advanced audio, utilising native code execution
for maximum performance, combined with a HLOS such as Linux or an RTOS such as
Imagination’s MeOS™ for ease of integration and function abstraction
· META LTP Embedded Controllers are single threaded, ultra-small 32-bit cores which
deliver full compatibility with other META processors in a negligible silicon
META cores are capable of up to 1GHz
operation on a 40G process, for a synthesised core. All the META cores are
fully synthesisable using readily available standard libraries. Imagination is
offering all members of the META Series2 family of SoC processors for licensing
More Detail on the META Family
hardware multi-threading delivers exceptional latency tolerance, and that
translates in real terms to getting 2x or more usable processing power compared
to conventional CPUs for similar silicon area, and often at lower clock speeds.
The single cycle context switching combined with other advanced interrupt and
low level hardware scheduling advances make META processors ideal for “”hard
real time”” applications, where high data rates and demanding high speed event
response mean single cycle context switch capability can make all the
difference. This plus the ability to uniquely combine DSP and RISC-like thread
configurations within a single unified engine allow designers to have a single embedded
processor that delivers all the high level application as well as highly
optimised DSP processing and real time performance demanded in many systems.
processors share common instruction sets, enabling easy migration from lower
end cores to higher end as system designs progress from one generation to the
next.,. This unique ability to use hardware multi-threading to create multiple
virtual processors also offers SoC systems designers the ability to consolidate
the various processing nodes used throughout the SoC under one consistent,
silicon efficient processor architecture.
SoCket™ means that designers can simply switch one META core for another with
little or no impact on the rest of the SoC design. Customers can start with a low
or mid-range META, then follow a logical upgrade curve to higher levels of
capability as experience with META and multi-threading grows and SoC architects
see the benefits of utilising META processors across multiple blocks in a SoC.
conventional processors are regularly stalled while waiting for memory requests
to complete, typically causing as much as 50%, of the processing resource to be
wasted. META’s unique implementation of multi-threading enables it to change
between hardware contexts each clock cycle, with up to four threads supported.
This means that while a memory request for a Linux application on one thread is
being resolved, an audio decoder can be progressed on another thread, data
progressed though a communications protocol stack on another, and real-time
hardware events serviced on another thread. Each thread sees the processor as
its own, creating in effect up to four virtual processors utilising a single
datapath. Caches can be configured to be coherent or as dedicated cache regions.
unique approach to embedded processor design enables META to deliver up to
twice the measurable throughput (e.g. Dhrystone) for the same clock speed and
silicon area to comparable, state-of-the-art conventional processors. The
scalability of the multithreaded META family delivers outstanding DMIPS for any
given silicon area and clock-speed, typically ranging from 220 for META LTP to
1610 DMIPS for HTP (at 65nm). Compared to other processor solutions META can
use a lower speed clock and less silicon area to deliver the same performance.
Indeed, in production META can deliver a demonstrable 2.4 DMIPS per MHz. By
utilising Imagination’s underlying architecture, which is built from the ground
up to support hardware multi-threading, META processors are ideally suited to
use in SoCs where high performance and sophisticated real time event handling
The META HTP family delivers the ultimate
combination of powerful general purpose 32-bit processor with high performance
DSP and low level control – all in a single, unified datapath and cache.
Capable of running many OS – and different OS on each thread if desired – the
META HTP is the perfect solution for embedded SoC processor resources. Most
configurations of HTP contain either 2 or 4 threads, with at least one
configured for DSP and at least one thread used for full Linux. META HTPhas optional double precision IEEE 754-2008 compliant floating point and
64-bit internal buses, loading a 64-bit word in a single cycle.
The META MTP family is designed to deliver
the benefits of multi-threading and high performance DSP. Typically configured
with two threads, META MTP processors have reduced ALU and cache resources to
minimise die size, and are usually using an RTOS or native execution for
applications. They are ideal for multimedia processing such as audio or
communications. META MTP cores are used in several of Imagination’s platform IP
solutions and IP cores, where a mix of low level control and DSP or other
mathematically intense processing tasks are required. Applications developed
for a META MTP can usually be moved to larger META HTP processors without
modification, offering an excellent upgrade path as applications mature and
expand. META MTPhas optional single
precision floating point and 32-bit internal buses.
The META LTP is a single threaded 32-bit workhorse
for deeply embedded control applications in SoCs. It is the ideal choice for
low-level control and data flow processing, and is used extensively in
Imagination’s own IP cores.
in a META can be configured to be either to be ‘GP (general purpose)’ or ‘DSP’.
The GP threads utilise a highly optimised RISC-like instruction set, with
smaller footprint instruction sets also available to minimise code size, and
can also run DSP code. Each DSP-tailored thread also adds ALU resources and
more registers to enable the processor to execute advanced DSP algorithms such
as audio codecs, modems and more with maximum performance.
processors run a wide range of operating systems, including full Linux (both
single processor and SMP), and Imagination’s own MeOS RTOS (Real Time Operating
System). Indeed, META is the only processor architecture able to support
multiple OS without the need for any virtualisation layer – the underlying architecture
inherently delivers this capability. META is highly suitable for porting other
high level open source OS such as Symbian or Android. Threads running low level
tasks can also be run natively without any OS for maximum efficiency. SMP Linux
enables the benefits of multi-processing and hardware multi-threading to be
brought together under a familiar Linux environment, enabling software
engineers to take advantage of many of the benefits of hardware multi-threading
without having to write any special code.
architecture throttles back aggressive code using AMA (Automatic MIPS
Allocation) which also enables the system designer to adjust what percentage of
total MIPS is made available to each thread. META can combine applications from
legacy developments while minimising the impact of ‘selfish software’ on other
threads. META’s superthreading feature enables threads to run simultaneously
provided they are not competing for the same resources, an approach with
significant benefits over superscalar architectures. Superthreading allows more
work per clock cycle so the SoC can run at lower clock speeds while AMA handles
system load-balancing to meet processing deadlines.
About Imagination Technologies
Technologies Group plc (LSE:IMG) – a global leader in multimedia and
communication silicon technologies – creates and licenses market-leading
processor cores for graphics, video, multi-threaded embedded processing/DSP and
multi-standard communications applications. These silicon intellectual property
(IP) solutions for systems-on-chip (SoC) are complemented by strong array
of software tools and drivers as well as extensive developer and
middleware ecosystems. Target markets includemobile phone, handheld multimedia, home consumer entertainment,
mobile and low-power computing, and in-car electronics.Its licensees include many of the leading semiconductor
and consumer electronics companies. Imagination has corporate headquarters in
the United Kingdom, with sales and R&D offices worldwide. See: www.imgtec.com.