Meeting end user demands
In modern SoC designs, the complexity and frequencies have steadily increased in order to meet the performance the end user demands; while power budgets and SoC area are paramount in order for a solution to be competitive. As our IP is adopted into more varied applications with a wider range of performance targets it is not unusual to find the GPU can be the dominant factor in the overall SoC floorplan, and the limiting factor in ultimate performance achieved. In addition to this the interaction between the physical properties of today’s advanced technology nodes and the functionality of the IP is key if these ever-increasing targets are to be met. An architecture that may have been simple to implement at lower speeds with lower bandwidth requirements can very quickly become impossible when aiming for today’s cutting edge performance.
It is no surprise that our customers, especially start-ups and smaller enterprises, often with little or no experience in back-end chip design can benefit from assistance in implementing our highly complex cores. This is where the Customer Engineering Layout team can help!
Benefits of watching:
- An introduction to the Customer Engineering Layout team – who we are and what we can do for you.
- Understand the interaction between the functional and the physical during the development of PowerVR IP cores.
- Gain an overview of how we push the Power Performance and Area (PPA) envelope to help guide you to the optimal position for your application.
- A look at the collateral available to help reduce your time to market.